Integrated circuit having an ESD protection structure and photon source

Patent metadata

Field	Value
Publication number	US-9953968-B2
Application number	US-201514628823-A
Country	US
Kind code	B2
Filing date	Feb 23, 2015
Priority date	Feb 28, 2014
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

An integrated circuit having an ESD protection structure is described. One embodiment includes a circuit section interconnected with a first terminal and with a second terminal and being operable at voltage differences between the first terminal and second terminal of greater than +10 V and less than −10 V. The integrated circuit additionally includes an ESD protection structure operable to protect the circuit section against electrostatic discharge between the first terminal and the second terminal. The ESD protection structure is operable with voltage differences between the first and second terminals of greater than +10 V and less than −10 V without triggering. The ESD protection structure is electrically and optically coupled to a photon source such that photons emitted by the photon source upon ESD pulse loading are absorbable in the ESD protection structure and an avalanche breakdown is initiatable by electron-hole pairs generated by the absorbed photons.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a circuit section interconnected with a first terminal and with a second terminal and operable at voltage differences between the first terminal and the second terminal of greater than +10 V and less than −10 V; and
an ESD protection structure operable to protect the circuit section against ESD loading between the first terminal and the second terminal,
wherein the ESD protection structure is operable with voltage differences between the first and second terminals of greater than +10 V and less than −10 V without triggering,
wherein the ESD protection structure is electrically and optically coupled to a photon source so that photons emitted by the photon source upon ESD loading are absorbable in the ESD protection structure and an avalanche breakdown is initiatable by electron-hole pairs generated by the absorbed photons,
wherein the integrated circuit comprises a differential transceiver.

2. The integrated circuit of claim 1 , wherein the ESD protection structure comprises two antiseries-interconnected ESD protection diodes.

3. The integrated circuit of claim 2 , wherein an ESD pulse is dissipatable in the ESD protection diodes in electrical breakdown operation of a pn junction between a p-type region and an n-type region.

4. The integrated circuit of claim 1 , wherein the ESD protection structure and the circuit section are operable at voltage differences between the first terminal and the second terminal of greater than +20 V and less than −20 V.

5. The integrated circuit of claim 1 , wherein the differential transceiver is a CAN transceiver and the circuit section is interconnected with one terminal from a CANH bus input/output terminal, a CANL bus input/output terminal, and ground as the first terminal, and with another terminal from the CANH bus input/output terminal, the CANL bus input/output terminal, and ground as the second terminal.

6. The integrated circuit of claim 1 , wherein the differential transceiver is a FlexRay transceiver, and the circuit section is interconnected with one terminal from a bus line positive terminal, a bus line negative terminal, and ground as the first terminal, and with another terminal from the bus line positive terminal, the bus line negative terminal, and ground as the second terminal.

7. An integrated circuit, comprising:
a circuit section interconnected with a first terminal and with a second terminal and operable at a positive voltage difference between the first terminal and second terminal of above +10 V; and
an ESD protection structure operable to protect the circuit section against electrostatic discharge between the first terminal and the second terminal,
wherein the ESD protection structure is operable with a positive voltage difference between the first and second terminals of above +10 V without triggering,
wherein the ESD protection structure is electrically and optically coupled to a photon source such that photons emitted by the photon source upon ESD pulse loading are absorbable in the ESD protection structure and an avalanche breakdown is initiatable by electron-hole pairs generated by the absorbed photons,
wherein a leakage current consumption between the first terminal and the second terminal at a specified positive maximum voltage is less than 100 nA and an input capacitance between the first terminal and the second terminal is less than 50 pF,
wherein the circuit section is a sensor interface.

8. The integrated circuit of claim 7 , wherein a specified negative absolute maximum voltage limit value between the first terminal and the second terminal is between −0.3 V and −1 V.

9. The integrated circuit of claim 7 , wherein a specified maximum positive operating voltage between the first terminal and the second terminal is greater than +20 V.

10. The integrated circuit of claim 9 , wherein the first terminal is an input terminal or an output terminal and the second terminal is a ground terminal.

11. The integrated circuit of claim 7 , wherein a first voltage V 1 between the first terminal and the second terminal, starting from which first voltage a current of at least 100 μA flows through the photon source, is between 60% and 120% of a second voltage V 2 , and the second voltage corresponds to an avalanche breakdown voltage of the ESD protection structure.

12. The integrated circuit of claim 7 , wherein at least one terminal of the ESD protection structure and a terminal of the photon source are electrically connected.

13. The integrated circuit of claim 7 , wherein the photons are emittable from the photon source as a result of charge carrier recombination of a pn junction operated in the forward direction in silicon.

14. The integrated circuit of claim 7 , wherein the photons are emittable from the photon source as a result of charge carrier acceleration of a pn junction operated in electrical breakdown in silicon.

15. The integrated circuit of claim 7 , wherein the photons are emittable from the photon source as a result of charge carrier acceleration in an electric field of a MOS channel operated in saturation, a MOS drain extension region, or a drain drift path in silicon.

16. The integrated circuit of claim 7 , wherein the ESD protection structure and the photon source are formed in a silicon semiconductor body with a distance of less than 50 μm.

17. The integrated circuit of claim 7 , wherein the ESD protection structure and the photon source are formed in a silicon semiconductor body with a distance of less than 200 μm and the photon source has a luminescence spectrum whose energy distribution has a peak in the range of 80% to 120% of the band gap energy of silicon.

18. The integrated circuit of claim 7 , wherein the photon source is electrically connected at at least one terminal to at least one of the first terminal, the second terminal, a central node of two antiseries-interconnected ESD diodes, an ESD secondary protection structure and the circuit section.

19. The integrated circuit of claim 7 , wherein the photon source is electrically and optically coupled to a plurality of ESD protection structures.

20. The integrated circuit of claim 7 , wherein the sensor interface is one of a Hall sensor interface, a buckle switch interface, a battery sensor interface, an active peripheral sensor interface, a distributed system interface, a peripheral sensor interface, a high-voltage sensor pin interface, a monitor pin sensor interface, a position sensor interface, or a switch feedback unit sensor interface.

21. The integrated circuit of claim 7 , wherein the first terminal is a terminal from a voltage sensor pin, a switch monitor pin, an input pin, or an output pin.

22. An integrated circuit, comprising:
a circuit section interconnected with a first terminal and with a second terminal and operable at voltage differences between the first terminal and the second terminal of greater than +10 V and less than −10 V; and
an ESD protection structure operable to protect the circuit section against ESD loading between the first terminal and the second terminal,
wherein the ESD protection structure is operable with voltage differences between the first and second terminals of greater than +10 V and less than −10 V without triggering,
wherein the ESD protection structure is electrically and optically coupled to a photon source so that photons emitted by the photon source upon ESD loading are absorbable in the ESD protection structure and an avalanche breakdown is ini

Assignees

• Infineon Technologies Ag

Inventors

• Cao Yiqun
• Glaser Ulrich
• Hell Magnus-Maria
• Lebon Julien
• Mayerhofer Michael
• Meiser Andreas
• Stecher Matthias
• Willemen Joost

Classifications

• H01L27/0292

  Electricity · mapped topic

• H01L27/0255 Primary

  Electricity · mapped topic

• H02H9/046

  responsive to excess voltage appearing at terminals of integrated circuits · CPC title

• H10D89/921

  characterised by the configuration of the interconnections connecting the protective arrangements, e.g. ESD buses · CPC title

• H10D89/611 Primary

  using diodes as protective elements · CPC title