Embedded graphite heat spreader for 3DIC

Patent metadata

Field	Value
Publication number	US-9953957-B2
Application number	US-201514639942-A
Country	US
Kind code	B2
Filing date	Mar 5, 2015
Priority date	Mar 5, 2015
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

A device with thermal control is presented. In some embodiments, the device includes a plurality of die positioned in a stack, each die including a chip, interconnects through a thickness of the chip, metal features of electrically conductive composition connected to the interconnects on a bottom side of the chip, and adhesive or underfill layer on the bottom side of the chip. At least one thermally conducting layer, which can be a pyrolytic graphite layer, a layer formed of carbon nanotubes, or a graphene layer, is coupled between a top side of one of the plurality of die and a bottom side of an adjoining die in the stack. A heat sink can be coupled to the thermally conducting layer.

First claim

What is claimed is:

1. A method of forming a stacked microelectronic device, comprising:
forming a plurality of die, each of the die with a thermally conducting sheet on a top side of a silicon chip, and with electrically insulating but thermally conducting material at one or more edges of the thermally conducting sheet;
stacking the plurality of die to form a stack such that the thermally conducting sheet of each of one or more of the die is disposed between the die, at least one die's electrically insulating but thermally conducting material electrically insulating the die's thermally conducting sheet from at least one interconnect that electrically connects the die to an overlying die in the stack;
mounting the stack of the plurality of die onto a substrate; and
mounting a heat sink to the stack of the plurality of die opposite the substrate.

2. A method of forming a stacked microelectronic device, comprising:
forming a plurality of die, each of the die with a thermally conducting sheet on a top side of a silicon chip;
stacking the plurality of die to form a stack such that the thermally conducting sheet of each of one or more of the die is disposed between the die;
mounting the stack of the plurality of die onto a substrate; and
mounting a heat sink to the stack of the plurality of die opposite the substrate;
wherein forming the plurality of die comprises, for at least one said die:
forming an adhesive layer on the top side of the die's silicon chip;
placing the die's thermally conducting sheet over the adhesive layer;
etching the die's thermally conducting sheet and the adhesive layer over a plurality of interconnects;
depositing an electrically insulating but thermally conducting layer over the die's thermally conducting sheet, with openings to expose the plurality of interconnects; and
metalizing to extend the plurality of interconnects through the adhesive layer, the die's thermally conducting sheet, and the electrically insulating but thermally conducting layer.

3. A method of forming a stacked microelectronic device, comprising:
forming a plurality of die, each of the die with a thermally conducting sheet on a top side of a silicon chip;
stacking the plurality of die to form a stack such that the thermally conducting sheet of each of one or more of the die is disposed between the die;
mounting the stack of the plurality of die onto a substrate; and
mounting a heat sink to the stack of the plurality of die opposite the substrate;
wherein the method further includes:
applying an electrically insulating but thermally conducting layer on a side wall of the stacked plurality of die such that the electrically insulating but thermally conducting layer on the side wall contacts each said thermally conducting sheet in the stack; and
mounting the stack on a substrate such that the electrically insulating but thermally conducting layer on the side wall connects with a heat path through the substrate.

4. The method of claim 3 , further including applying a metal layer over the electrically insulating but thermally conducting layer on the side wall.

5. The method of claim 1 , further including
attaching solder balls to at least one of the silicon chips for interconnecting the stacked microelectronic device to the substrate.

6. The method of claim 2 wherein at least one said thermally conducting sheet is a pyrolytic graphite sheet.

7. A method of forming a microelectronic device, the method comprising:
providing a first integrated circuit with circuitry;
forming a first layer over the first integrated circuit, with at least one of properties (i) and (ii) being true with regard to a thermal conductivity of the first layer in at least one lateral direction:
(i) the first layer comprises a metal, and said thermal conductivity is at least as high as a thermal conductivity of a layer of such metal in at least one lateral direction;
(ii) the first layer comprises carbon, and said thermal conductivity is at least as high as a thermal conductivity of a layer of such carbon in at least one lateral direction;
forming one or more first vias each of which passes through the first layer and exposes a corresponding first region of the circuitry of the first integrated circuit;
attaching a second integrated circuit comprising circuitry to the first integrated circuit, at least part of the first layer lying between the first and second integrated circuits, the circuitry of the second integrated circuit being electrically connected to each first region by a corresponding electrical connection reaching the first region through the corresponding first via;
after forming the one or more first vias but before attaching the second integrated circuit, forming an electrically insulating layer over the first layer.

8. The method of claim 7 wherein each said electrical connection lies over the circuitry of the first integrated circuit and under the circuitry of the second integrated circuit.

9. The method of claim 7 wherein the first layer comprises a pyrolytic graphite layer.

10. The method of claim 7 wherein the first layer comprises a graphene layer.

11. The method of claim 7 wherein the first layer comprises a carbon nanotube layer.

12. The method of claim 7 wherein the first layer comprises a metal layer.

13. The method of claim 7 further comprising, after forming the electrically insulating layer but before attaching the second integrated circuit, forming a conductive feature on each first region, each conductive feature being electrically insulated from the first layer by the electrically insulating layer;
wherein attaching the second integrated circuit comprises attaching the second integrated circuit to each said conductive feature.

14. The method of claim 7 wherein the electrically insulating layer is at least as thermally conducting as diamond-like carbon.

15. The method of claim 7 wherein the electrically insulating layer comprises diamond-like carbon.

16. The method of claim 7 further comprising, after attaching the second integrated circuit, forming a thermally conductive layer on a sidewall of a structure comprising the first and second integrated circuits.

17. The method of claim 16 wherein the thermally conductive layer is at least as thermally conductive as diamond-like carbon.

18. The method of claim 17 wherein the thermally conductive layer is diamond-like carbon.

19. The method of claim 1 wherein said at least one die's electrically insulating but thermally conducting material electrically insulates the die's thermally conducting sheet from each of a plurality of laterally-spaced-apart interconnects each of which electrically connects the die to the overlying die.

Assignees

• Invensas Corp

Inventors

• Gao Guilian
• Woychik Charles G
• Uzoh Cyprian Emeka
• Wang Liang

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title