Semiconductor structure and manufacturing method thereof

US9953936B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9953936-B2
Application numberUS-201514928651-A
CountryUS
Kind codeB2
Filing dateOct 30, 2015
Priority dateOct 30, 2015
Publication dateApr 24, 2018
Grant dateApr 24, 2018

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  1. Title

    What the patent document calls the invention.

  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor structure includes a transceiver configured to communicate with a device, a molding surrounding the transceiver, a via extending through the molding, an insulating layer disposed over the molding, the via and the transceiver, and a redistribution layer (RDL) disposed over the insulating layer and comprising an antenna and a dielectric layer surrounding the antenna, wherein a portion of the antenna is extended through the insulating layer and the molding to electrically connect with the transceiver.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor structure, comprising: a transceiver configured to communicate with a device; a molding surrounding the transceiver; a via extending through the molding; an insulating layer disposed over the molding, the via and the transceiver; and a redistribution layer (RDL) disposed over the insulating layer and comprising an antenna and a dielectric layer surrounding the antenna, wherein a portion of the antenna is extended through the insulating layer and the molding and is electrically connected with the transceiver. 2. The semiconductor structure of claim 1 , wherein the via is configured to inductively coupled with the antenna. 3. The semiconductor structure of claim 1 , wherein the via is in spiral, loop, rectangular, circular or polygonal configuration. 4. The semiconductor structure of claim 1 , wherein the via has a depth of about 100 um to about 200 um. 5. The semiconductor structure of claim 1 , wherein the antenna has a resonance frequency of about 2.4 GHz. 6. The semiconductor structure of claim 1 , wherein the antenna is configured to transmit or receive a signal in a Bluetooth low energy (BLE) or in a predetermined electromagnetic frequency of about 2.4 GHz. 7. The semiconductor structure of claim 1 , wherein the antenna has a length of about 200 um and a width of about 10 um. 8. The semiconductor structure of claim 1 , wherein the insulating layer has a thickness of about 3 um to about 5 um. 9. The semiconductor structure of claim 1 , wherein the antenna is configured to transmit a signal reaching a distance of greater than about 8 meters. 10. The semiconductor structure of claim 1 , further comprising a charger surrounded by the molding and configured to convert a charging power from AC to DC. 11. The semiconductor structure of claim 1 , further comprising a resonator configured to generate a signal to the charger. 12. The semiconductor structure of claim 1 , wherein the antenna comprise a first elongated portion extending over the insulating layer and a first via portion extending through the insulating layer. 13. The semiconductor structure of claim 12 , wherein the RDL further comprises at least one interconnect structure disposed in the dielectric layer. 14. The semiconductor structure of claim 13 , wherein the interconnect structure comprises a second elongated portion extending over the insulating layer and a second via portion extending through the insulating layer.

Assignees

Inventors

Classifications

  • the semiconductor body being completely enclosed · CPC title

  • the encapsulations exposing the passive side of the semiconductor body · CPC title

  • on encapsulations · CPC title

  • for antennas · CPC title

  • Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

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Frequently asked questions

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What does patent US9953936B2 cover?
A semiconductor structure includes a transceiver configured to communicate with a device, a molding surrounding the transceiver, a via extending through the molding, an insulating layer disposed over the molding, the via and the transceiver, and a redistribution layer (RDL) disposed over the insulating layer and comprising an antenna and a dielectric layer surrounding the antenna, wherein a por…
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W44/20. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 24 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).