System on chip and corresponding monitoring method

Patent metadata

Field	Value
Publication number	US-9952963-B2
Application number	US-201314078960-A
Country	US
Kind code	B2
Filing date	Nov 13, 2013
Priority date	Nov 14, 2012
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

The present invention relates to aSoC, which includes a master device, a slave device, a high-speed bus, and a monitoring apparatus. The master device is connected to a first port of the high-speed bus, and the slave device is connected to a second port of the high-speed bus, so that the master device is capable of accessing the slave device. The monitoring apparatus is arranged between the first port of the high-speed bus and the master device, and/or between the second port of the high-speed bus and the slave device, and configured to record, based on a high-speed bus communication protocol, state information of each command that passes through the first port and/or the second port, and when state information of a command indicates that an operation of the command is in a timeout state, report an interrupt to locate a faulty node on the high-speed bus.

First claim

What is claimed is:

1. A system on chip, comprising:
a master device;
a slave device;
a high-speed bus; and
a monitoring apparatus, wherein:
the master device interfaces to the high-speed bus through a first port of the high-speed bus, and the slave device interfaces to the high-speed bus through a second port of the high-speed bus, so that the master device is capable of accessing the slave device; and
the monitoring apparatus is arranged between the first port of the high-speed bus and the master device, and/or between the second port of the high-speed bus and the slave device, and configured to record, based on a high-speed bus communication protocol, state information of each command that passes through the first port and/or the second port, and when state information of a command indicates that an operation of the command is in a timeout state, report an interrupt to locate a faulty node on the high-speed bus, the monitoring apparatus comprising:
a read buffer to record state information of a read command assigned to the read buffer;
a write buffer to record state information of a write command assigned to the write buffer;
a controller, respectively in communication with the read buffer and the write buffer to control the read buffer and/or the write buffer to complete, in a virtual manner, a read command and/or a write command that is uncompleted by the master device or slave device; and
a reset, respectively in communication with the read buffer and the write buffer to reset the read buffer and/or the write buffer; and
the read buffer and/or the write buffer respectively records the state, an identity number, an uncompleted data amount, and an operation order of a command assigned to the buffer.

2. The system on chip according to claim 1 , wherein after the monitoring apparatus reports an interrupt to locate a faulty node on the high-speed bus, the monitoring apparatus at the node replaces the corresponding master device or slave device to complete, in a virtual manner, the command in the timeout state, and performs a reset operation on the corresponding master device or slave device.

3. The system on chip according to claim 1 , wherein: the monitoring apparatus is further connected to a debug bus and configured to export the state information of each command that is recorded by the monitoring apparatus, so that the state information of each command that is recorded by the monitoring apparatus is stored.

4. The system on chip according to claim 1 , wherein: at the port of the high-speed bus, a bus trace apparatus is further arranged to record each command that passes through the port, wherein the bus trace apparatus works with the monitoring apparatus to record each command that passes through the port and state information of each command.

5. A system on chip, comprising a master device, a slave device, a high-speed bus, and a monitoring apparatus, wherein:
the master device is connected to a first port of the high-speed bus, and the slave device is connected to a second port of the high-speed bus, so that the master device is capable of accessing the slave device;
the monitoring apparatus is arranged between the first port of the high-speed bus and the master device, and/or between the second port of the high-speed bus and the slave device, and configured to record, based on a high-speed bus communication protocol, state information of each command that passes through the first port and/or the second port, and when state information of a command indicates that an operation of the command is in a timeout state, report an interrupt to locate a faulty node on the high-speed bus;
after the monitoring apparatus reports an interrupt to locate a faulty node on the high-speed bus, the monitoring apparatus at the node replaces the corresponding master device or slave device to complete, in a virtual manner, the command in the timeout state, and performs a reset operation on the corresponding master device or slave device;
the monitoring apparatus comprises:
a read buffer module, comprising at least one read buffer configured to record state information of a read command assigned to the read buffer;
a write buffer module, comprising at least one write buffer configured to record state information of a write command assigned to the write buffer;
a control module, respectively connected to the read buffer module and the write buffer module to control the read buffer in the read buffer module and/or the write buffer in the write buffer module to complete, in a virtual manner, a read command and/or a write command that is uncompleted by the master device or slave device; and
a resetting module, respectively connected to the read buffer module and the write buffer module to reset the read buffer in the read buffer module and/or the write buffer in the write buffer module; and

each buffer in the read buffer in the read buffer module and/or the write buffer in the write buffer module respectively records the state, an identity number, an uncompleted data amount, and an operation order of a command assigned to the buffer.

6. The system on chip according to claim 5 , wherein the number of the read buffers in the read buffer module and the number of the write buffers in the write buffer module are respectively equal to a maximum number of uncompleted commands that is supported by the first port and a maximum number of uncompleted commands that is supported by the second port, and the maximum number of uncompleted commands that is supported by the first port is equal to the maximum number of uncompleted commands that is supported by the second port.

7. The system on chip according to claim 6 , wherein an input of the monitoring apparatus comprises first port information/second port information, and an output of the monitoring apparatus comprises state information of each command assigned to each buffer therein and the reported interrupt.

8. The system on chip according to claim 7 , wherein the first port information/second port information comprises a read/write command, read/write data, a write response, or a read response.

9. The system on chip according to claim 7 , wherein the state information of each command assigned to each buffer comprises a read/write timeout interrupt, a read/write command timeout state, a read/write buffer state, a read/write command state, a read/write command order, read/write command identity number information, read/write command address information, a signal generated by simulating the master/slave device when the master/slave device is reset, and a read/write command delay.

10. The system on chip according to claim 7 , wherein the monitoring apparatus assigns each command to each buffer therein, so that each buffer respectively records state information of the assigned command, wherein commands of different identities are respectively assigned to different buffers, and when different commands of a same identity number are assigned to different buffers, a corresponding operation order is further assigned in sequence to identify the order of the different commands of the same identity.

11. The system on chip according to claim 7 , wherein the buffer comprises:
a command valid sending unit, configured to record whether a command assigned to the buffer is validly written to the buffer;
a command state unit, configured to record whether state information of the command assigned to the buffer is occupied or idle;
a command identity number storage unit, configured to record an identity number of the command assigned to the buffer;
a command operation order unit, configured to record an operation order of the command assigned to the buffer;
an uncompleted data am

Assignees

• Huawei Tech Co Ltd

Inventors

• Mou Chenglei
• Han Qi

Classifications

• G06F11/348

  Circuit details, i.e. tracer hardware · CPC title

• G06F11/3648

  using additional hardware · CPC title

• G06F11/3027

  where the computing system component is a bus · CPC title

• G06F11/349

  for interfaces, buses · CPC title

• G06F11/364 Primary

  tracing values on a bus · CPC title