Accelerated address indirection table lookup for wear-leveled non-volatile memory

Patent metadata

Field	Value
Publication number	US-9952801-B2
Application number	US-201514752554-A
Country	US
Kind code	B2
Filing date	Jun 26, 2015
Priority date	Jun 26, 2015
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

Embodiments are generally directed to accelerated address indirection table lookup for wear-leveled non-volatile memory. A embodiment of a memory device includes nonvolatile memory; a memory controller; and address indirection logic to provide address indirection for the nonvolatile memory, of the address indirection logic to maintain an address indirection table (AIT) in the nonvolatile memory, the AIT including a plurality of levels, and copy at least a portion of the AIT to a second memory, the second memory having less latency than the first memory.

First claim

What is claimed is:

1. A memory device comprising:
a nonvolatile memory;
a memory controller; and
address indirection logic to provide address indirection for the nonvolatile memory, wherein to provide address indirection, the address indirection logic is to:
maintain an address indirection table (AIT) in the nonvolatile memory, the AIT including a plurality of levels, and
copy at least a portion of the AIT to a second memory, the second memory having less latency than the nonvolatile memory;

wherein the memory controller includes AIT caches, the AIT caches including a cache for each level of the AIT stored in the nonvolatile memory; and
wherein, upon a miss in a translation lookaside buffer (TLB) for the nonvolatile memory, a lookup of the nonvolatile memory is to include a lookup of the copy of the AIT in the second memory.

2. The memory device of claim 1 , wherein upon a miss or error in one or more levels of the AIT in the second memory, a lookup of the nonvolatile memory is to include a lookup of at least one of the AIT caches.

3. The memory device of claim 1 , wherein the nonvolatile memory is subject to wear leveling, the wear leveling including a portion of the nonvolatile memory that stores the AIT.

4. The memory device of claim 3 , wherein the AIT stored in the nonvolatile memory and the AIT stored in the second memory are each to be updated upon a wear level move.

5. The memory device of claim 1 , wherein the at least a portion of the AIT copied to the second memory includes a last level of the AIT.

6. The memory device of claim 1 , wherein the second memory comprises dynamic random access memory (DRAM).

7. A method comprising:
storing a copy of one or more levels of an address indirection table (AIT) of a nonvolatile memory into a second memory, the second memory comprising a volatile memory;
caching address entries for each level of the AIT in AIT caches of a memory controller for the nonvolatile memory;
receiving a request for an address of the nonvolatile memory; and performing a lookup of the address including:
performing a lookup of an address in the nonvolatile memory,
upon the address lookup resulting in a miss, performing a lookup of the AIT stored in the volatile memory, and
upon a miss in a translation lookaside buffer (TLB) for the nonvolatile memory, the lookup of the nonvolatile memory to include a lookup of the copy of the one or more levels of the AIT in the second memory.

8. The method of claim 7 , further comprising performing wear leveling of the nonvolatile memory, wherein the performance of wear leveling includes wear leveling of memory locations of the AIT stored in the nonvolatile memory.

9. The method of claim 8 , further comprising updating the AIT in the nonvolatile memory and the AIT stored in the volatile memory upon a wear level move in the performance of the wear leveling.

10. The method of claim 7 , wherein the storing of the last level of the AIT of the nonvolatile memory into the volatile memory is performed upon power up of a system including the nonvolatile memory.

11. The method of claim 7 , wherein the storing of the one or more levels of the AIT includes storing a last level of the AIT.

12. The method of claim 7 , wherein the volatile memory comprises dynamic random access memory (DRAM).

13. A computing system comprising:
a network interface;
a central processing unit (CPU) to process data and instructions and communicatively coupled with the network interface;
a volatile memory, the volatile memory including a main memory to store data and instructions for processing; and
a nonvolatile memory device including:
nonvolatile memory,
a memory controller, and
address indirection logic to provide address indirection for the nonvolatile memory, wherein the address indirection logic is to:
maintain an address indirection table (AIT) in the nonvolatile memory, the AIT including a plurality of levels, and
copy one or more levels of the AIT to a shadow table in a portion of the volatile memory;

wherein the memory controller includes AIT caches, the AIT caches including a cache for each level of the AIT stored in the nonvolatile memory; and wherein, upon a miss in a translation lookaside buffer (TLB) for the nonvolatile memory, a lookup of the nonvolatile memory is to include a lookup of the copy of the one or more levels of the AIT in the shadow table in the volatile memory.

14. The computing system of claim 13 , wherein the portion of the volatile memory is not included within the main memory.

15. The computing system of claim 13 , wherein upon a miss or error in the shadow table, a lookup of the nonvolatile memory is to include a lookup of at least one of the AIT caches.

16. The computing system of claim 13 , wherein the nonvolatile memory is subject to wear leveling, the wear leveling including a portion of the nonvolatile memory that stores the AIT.

17. At least one non-transitory computer-readable storage medium having stored thereon data representing sequences of instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising:
storing a copy of one or more levels of an address indirection table (AIT) of a nonvolatile memory into a second memory, the second memory comprising a volatile memory;
caching address entries for each level of the AIT in AIT caches of a memory controller for the nonvolatile memory;
receiving a request for an address of the nonvolatile memory; and performing a lookup of the address including:
performing a lookup of an address in the nonvolatile memory, upon the address lookup resulting in a miss, performing a lookup of the AIT stored in the volatile memory, and upon a miss in a translation lookaside buffer (TLB) for the nonvolatile memory, the lookup of the nonvolatile memory to include a lookup of the copy of the one or more levels of the AIT in the second memory.

18. The medium of claim 17 , further comprising instructions that, when executed by the one or more processors, cause the one or more processors to perform operations comprising:
performing wear leveling of the nonvolatile memory, wherein the performance of wear leveling includes wear leveling of a portion of the nonvolatile memory that stores the AIT.

Assignees

• Intel Corp

Inventors

• Ramanujan Raj K
• Zhu Jun
• Arafa Mohamed
• Han Woojong
• Horwich Jordan A

Classifications

• G06F12/1027 Primary

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F12/1009

  using page tables, e.g. page table structures · CPC title

• G06F3/0649 Primary

  Lifecycle management · CPC title

• G06F3/0685 Primary

  Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays · CPC title

• G06F2212/22

  Employing cache memory using specific memory technology · CPC title