MEMS structure with improved shielding and method

Patent metadata

Field	Value
Publication number	US-9950921-B2
Application number	US-201514930642-A
Country	US
Kind code	B2
Filing date	Nov 2, 2015
Priority date	Mar 7, 2013
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

An integrated circuit includes a substrate member having a surface region and a CMOS IC layer overlying the surface region. The CMOS IC layer has at least one CMOS device. The integrated circuit also includes a bottom isolation layer overlying the CMOS IC layer, a shielding layer overlying a portion of the bottom isolation layer, and a top isolation layer overlying a portion of the bottom isolation layer. The bottom isolation layer includes an isolation region between the top isolation layer and the shielding layer. The integrated circuit also has a MEMS layer overlying the top isolation layer, the shielding layer, and the bottom isolation layer. The MEMS layer includes at least one MEMS structure having at least one movable structure and at least one anchored structure. The at least one anchored structure is coupled to a portion of the top isolation layer, and the at least one movable structure overlies the shielding layer.

First claim

What is claimed is:

1. An integrated circuit comprising:
a substrate member having a surface region;
a CMOS IC layer overlying the surface region, the CMOS IC layer having a plurality of CMOS integrated circuits;
a bottom isolation layer made entirely of a first dielectric material overlying the CMOS IC layer;
a conductive shielding layer overlying a portion of the bottom isolation layer;
a top isolation layer made entirely of a second dielectric material disposed directly on a portion of the bottom isolation layer, wherein the bottom isolation layer comprises an isolation region between the top isolation layer and the conductive shielding layer, the isolation region extending to a sidewall of the top isolation region such that no conductive layer is adjacent to the sidewall of the top isolation region; and
a MEMS layer overlying the top isolation layer, the shielding layer, and the bottom isolation layer,
the MEMS layer including at least one MEMS structure having at least one movable structure and at least one anchored structure, the at least one movable structure being separated from the at least one anchored structure, wherein the at least one anchored structure is coupled to a portion of the top isolation layer, wherein the at least one movable structure overlies the shielding layer.

2. The integrated circuit of claim 1 wherein the shielding layer is disposed within a portion of the bottom isolation layer.

3. The integrated circuit of claim 1 wherein the shielding layer comprises a single-sided partial shielding layer underlying at least a portion of the movable structure.

4. The integrated circuit of claim 1 wherein the shielding layer comprises a full shielding layer underlying at least a portion of the movable structure and at least a portion of the anchored structure.

5. The integrated circuit of claim 4 wherein the isolation region is configured to separate the top isolation layer from the shielding layer.

6. The integrated circuit of claim 1 wherein the shielding layer comprises a polysilicon material or an aluminum material.

7. The integrated circuit of claim 1 wherein the shielding layer is underneath a gap between the at least one movable structure and at least one anchored structure.

8. The integrated circuit of claim 1 wherein the at least one MEMS structure comprises an accelerometer, a gyrometer, a magnetometer, or a pressure sensor.

9. An integrated circuit comprising: a substrate member having a surface region; a CMOS IC layer overlying the surface region, the CMOS IC layer having a plurality of CMOS integrated circuits; a bottom isolation layer made entirely of a first dielectric material overlying the CMOS IC layer; a shielding layer overlying a portion of the bottom isolation layer; a top isolation layer made entirely of a second dielectric material disposed directly on a portion of the bottom isolation layer, wherein the bottom isolation layer comprises an isolation region between the top isolation layer and the shielding layer, the isolation region being an exposed portion of the bottom isolation layer free from conductive contact with sidewall of the top isolation layer and the shielding layer; and a MEMS layer overlying the top isolation layer, the shielding layer, and the bottom isolation layer, the MEMS layer including at least one MEMS structure having at least one movable structure and at least one anchored structure, wherein the at least one anchored structure is coupled to a portion of the top isolation layer, wherein the at least one movable structure is separate from the at least one anchored structure and overlies the shielding layer.

10. The integrated circuit of claim 9 wherein the shielding layer is formed within a portion of the bottom isolation layer.

11. The integrated circuit of claim 9 wherein the shielding layer comprises a single-sided partial shielding layer underlying at least a portion of the movable structure.

12. The integrated circuit of claim 9 wherein the shielding layer comprises a full shielding layer underlying at least a portion of the movable structure and at least a portion of the anchored structure.

13. The integrated circuit of claim 12 wherein the isolation region is configured to separate the top isolation layer from the shielding layer.

14. The integrated circuit of claim 9 wherein the shielding layer comprises a polysilicon material or an aluminum material.

15. The integrated circuit of claim 9 wherein the shielding layer is underneath a gap between the at least one movable structure and at least one anchored structure.

16. The integrated circuit of claim 9 wherein the at least one MEMS structure comprises an accelerometer, a gyrometer, a magnetometer, or a pressure sensor.

Assignees

• Mcube Inc

Inventors

• Lee Te-Hsi “Terrence”
• Sridharamurthy Sudheer S
• Yoneoka Shingo
• Zhang Wenhua

Classifications

• B81C1/0038

  Processes for creating layers of materials not provided for in groups B81C1/00357 - B81C1/00373 · CPC title

• B81B2203/0118

  Cantilevers · CPC title

• B81B7/0022 Primary

  Protection against electrostatic discharge (circuit arrangements for protecting electronic switching circuits used for pulse technique against overcurrent or overvoltage H03K17/08; electrostatic discharge protection for electronic semiconductor circuits H10D89/60) · CPC title

• B81B3/0086

  Electrical characteristics, e.g. reducing driving voltage, improving resistance to peak voltage · CPC title

• B81C1/00246 Primary

  Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate · CPC title