High-speed level-shifting multiplexer

Patent metadata

Field	Value
Publication number	US-2016134286-A1
Application number	US-201414534967-A
Country	US
Kind code	A1
Filing date	Nov 6, 2014
Priority date	Nov 6, 2014
Publication date	May 12, 2016
Grant date	—

Abstract

Systems and methods for level-shifting multiplexing are described herein. In one embodiment, a method for level-shifting multiplexing comprises selecting one of a plurality of inputs based on one or more select signals, and pulling down one of first and second nodes based on a logic state of the selected one of the plurality of inputs. The method also comprises pulling up the first node if the second node is pulled down, and pulling up the second node if the first node is pulled down.

First claim

What is claimed is:

1 . A level-shifting multiplexer, comprising:
a first pull-down circuit coupled to a first node and having first and second inputs, wherein the first pull-down circuit is configured to select one of the first and second inputs based on one or more select signals, to pull down the first node if the first input is selected and driven to a first state, and to pull down the first node if the second input is selected and driven to a second state; a second pull-down circuit coupled to a second node and having third and fourth inputs, wherein the second pull-down circuit is configured to select one of the third and fourth inputs based on the one or more select signals, to pull down the second node if the third input is selected and driven to a third state, and to pull down the fourth node if the fourth input is selected and driven to a fourth state; and a pull-up circuit configured to pull up the first node if the second node is pulled down by the second pull-down circuit, and to pull up the second node if the first node is pulled down by the first pull-down circuit.

2 . The level-shifting multiplexer of claim 1 , wherein each of the first, second, third and fourth states is a logic one state.

3 . The level-shifting multiplexer of claim 2 , wherein the first and third inputs are driven by a first pair of complementary signals, and the second and fourth inputs are driven by a second pair of complementary signals.

4 . The level-shifting multiplexer of claim 1 , wherein the pull-up circuit comprises:
a first transistor configured to pull up the first node if the second node is pulled down by the second pull-down circuit, wherein the first transistor has a gate coupled to the second node; and a second transistor configured to pull up the second node if the first node is pulled down by the first pull-down circuit, wherein the second transistor has a gate coupled to the first node.

5 . The level-shifting multiplexer of claim 4 , wherein the first and second transistors comprise cross-coupled p-type metal-oxide-semiconductor (PMOS) transistors.

6 . The level-shifting multiplexer of claim 4 , further comprising a choke circuit configured to reduce current from a supply rail to the first transistor if the first input is selected and driven to the first state.

7 . The level-shifting multiplexer of claim 6 , wherein the choke circuit is configured to reduce current from the supply rail to the first transistor if the second input is selected and driven to the second state.

8 . The level-shifting multiplexer of claim 6 , wherein the choke circuit is configured to reduce current from the supply rail to the second transistor if the third input is selected and driven to the third state.

9 . The level-shifting multiplexer of claim 1 , further comprising a clamp transistor coupled between the second node and a ground, wherein the clamp transistor is configured to turn on if a disable signal is in a logic one state.

10 . A method for level-shifting multiplexing, comprising:
selecting one of a plurality of inputs based on one or more select signals; pulling down one of first and second nodes based on a state of the selected one of the plurality of inputs; pulling up the first node if the second node is pulled down; and pulling up the second node if the first node is pulled down.

11 . The method of claim 10 , wherein each of the plurality of inputs comprises a differential input.

12 . The method of claim 11 , wherein pulling up the first node if the second node is pulled down comprises pulling up the first node to a first voltage, wherein the selected one of the plurality of inputs is driven by a differential signal having a voltage swing approximately equal to a second voltage and the first voltage is greater than the second voltage.

13 . The method of claim 10 , wherein pulling up the first node if the second node is pulled down comprises pulling up the first node using a first transistor coupled between a supply rail and the first node, and pulling up the second node if the first node is pulled down comprises pulling up the second node using a second transistor coupled between the supply rail and the second node.

14 . The method of claim 13 , further comprising choking current from the supply rail to the first transistor if the first node is pulled down.

15 . The method of claim 14 , further comprising choking current from the supply rail to the second transistor if the second node is pulled down.

16 . An apparatus for level-shifting multiplexing, comprising:
means for selecting one of a plurality of inputs based on one or more select signals; means for pulling down one of first and second nodes based on a state of the selected one of the plurality of inputs; means for pulling up the first node if the second node is pulled down; and means for pulling up the second node if the first node is pulled down.

17 . The apparatus of claim 16 , wherein each of the plurality of inputs comprises a differential input.

18 . The apparatus of claim 17 , wherein the means for pulling up the first node if the second node is pulled down comprises means for pulling up the first node to a first voltage, wherein the selected one of the plurality of inputs is driven by a differential signal having a voltage swing approximately equal to a second voltage and the first voltage is greater than the second voltage.

19 . The apparatus of claim 16 , wherein the means for pulling up the first node if the second node is pulled down comprises means for pulling up the first node using a first transistor coupled between a supply rail and the first node, and the means for pulling up the second node if the first node is pulled down comprises means for pulling up the second node using a second transistor coupled between the supply rail and the second node.

20 . The apparatus of claim 19 , further comprising means for choking current from the supply rail to the first transistor if the first node is pulled down.

21 . The apparatus of claim 20 , further comprising means for choking current from the supply rail to the second transistor if the second node is pulled down.

22 . A multiplexer, comprising:
a first level-shifting multiplexer configured to select one of a first plurality of inputs based on a first plurality of select signals, to level shift a signal at the selected one of the first plurality of inputs, and to output the level-shifted signal of the first level-shifting multiplexer at a first output; a second level-shifting multiplexer configured to select one of a second plurality of inputs based on a second plurality of select signals, to level shift a signal at the selected one of the second plurality of inputs, and to output the level-shifted signal of the second level-shifting multiplexer at a second output; a combining circuit configured to combine the first and second outputs; and a decoder configured to select one of the first and second plurality of inputs based on a pointer by either setting one of the first plurality of select signals to a first state and disabling the second level-shifting multiplexer or setting one of the second plurality of select signals to a second state and disabling the first level-shifting multiplexer.

23 . The multiplexer of claim 21 , wherein each of the first and second states is a logic one state.

24 . The multiplexer of claim 21 , wherein the combining circuit is configured to

Assignees

• Qualcomm Inc

Inventors

• Bowles Kevin Robert
• Corona Jose Gabriel
• Boynapalli Venugopal

Classifications

• H03K3/35613 Primary

  the input circuit having a differential configuration · CPC title

• H03K17/002

  Switching arrangements with several input- or output terminals (code converters H03M5/00, H03M7/00) · CPC title

• H03K17/005

  with several inputs only · CPC title

• H03K19/018507 Primary

  Interface arrangements · CPC title

• H03K19/018528 Primary

  with at least one differential stage · CPC title