Device stack with novel gate capacitor topology

Patent metadata

Field	Value
Publication number	US-9948252-B1
Application number	US-201715481276-A
Country	US
Kind code	B1
Filing date	Apr 6, 2017
Priority date	Apr 6, 2017
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

Systems, methods and apparatus for practical realization of an integrated circuit comprising a stack of transistors operating as an RF amplifier are described. As stack height is increased, capacitance values of gate capacitors used to provide a desired distribution of an RF voltage at the output of the amplifier across the stack may decrease to values approaching parasitic/stray capacitance values present in the integrated circuit which may render the practical realization of the integrated circuit difficult. Coupling of an RF gate voltage at the gate of one transistor of the stack to a gate of a different transistor of the stack can allow for an increase in the capacitance value of the gate capacitor of the different transistor for obtaining an RF voltage at the gate of the different transistor according to the desired distribution.

First claim

The invention claimed is:

1. A monolithically integrated circuital arrangement comprising:
a stack of a plurality of transistors arranged in a cascode configuration, comprising an input transistor and N cascode transistors comprising an output transistor, N being an integer equal to or larger than two, the stack configured to operate between a supply voltage provided at a drain of the output transistor and a reference voltage provided at a source of the input transistor;
N gate capacitors, each gate capacitor of the N gate capacitors connected, at a first terminal of the each gate capacitor, to a gate of a respective transistor of the N cascode transistors, wherein at least one gate capacitor of the N gate capacitors is connected, at a second terminal of the at least one gate capacitor, to a first terminal of a coupling gate capacitor of the N gate capacitors, and remaining gate capacitors of the N gate capacitors are connected, at a second terminal of each gate capacitor of the remaining gate capacitors, to the reference voltage.

2. The monolithically integrated circuital arrangement according to claim 1 , wherein:
the arrangement is configured to operate as a radio frequency (RF) amplifier that provides an amplified version of an RF signal at a gate of the input transistor to a gate of the output transistor, and
each gate capacitor of the N gate capacitors is configured to control an RF voltage amplitude at the gate of the respective transistor based on an RF voltage at a drain of the respective transistor and a desired distribution of the RF voltage across the stack.

3. The monolithically integrated circuital arrangement according to claim 2 , wherein the RF voltage amplitude at the gate of the respective transistor of the at least one gate capacitor is further controlled by the coupling gate capacitor.

4. The monolithically integrated circuital arrangement according to claim 2 , wherein:
the coupling gate capacitor is configured to provide a portion of the RF voltage amplitude at the gate of the respective transistor,
the at least one gate capacitor is configured to provide a remaining portion of the RF voltage amplitude, and
the remaining portion of the RF voltage amplitude is inversely proportional to a capacitance value of the at least one gate capacitor.

5. The monolithically integrated circuital arrangement according to claim 4 , further comprising an additional gate capacitor connected between the gate of the respective transistor of the at least one gate capacitor and the reference voltage.

6. The monolithically integrated circuital arrangement according to claim 1 , wherein the integer N is equal to or greater than 5.

7. The monolithically integrated circuital arrangement according to claim 6 , wherein the respective transistor of the at least one gate capacitor is the output transistor.

8. The monolithically integrated circuital arrangement according to claim 2 , wherein the desired distribution of the RF voltage across the stack is a substantially equal division of the RF voltage across the stack.

9. The monolithically integrated circuital arrangement according to claim 2 , wherein the desired distribution of the RF voltage across the stack is an unequal division of the RF voltage across the stack.

10. The monolithically integrated circuital arrangement according to claim 1 , wherein the plurality of transistors are metal-oxide-semiconductor (MOS) field effect transistors (FETs), or complementary metal-oxide-semiconductor (CMOS) field effect transistors (FETs).

11. The monolithically integrated circuital arrangement according to claim 10 , wherein the plurality of transistors are fabricated using one of: a) silicon-on-insulator (SOI) technology, and b) silicon-on-sapphire technology (SOS).

12. The monolithically integrated circuital arrangement according to claim 2 , further comprising N resistors, each resistor of the N resistors connected, at a first terminal of the each resistor, to the first terminal of a respective gate capacitor of the N gate capacitors,
wherein an impedance of the each resistor is adapted to substantially isolate the RF voltage at the gate of the respective transistor coupled to the first terminal of the each transistor from a second terminal of the each resistor.

13. The monolithically integrated circuital arrangement according to claim 1 , wherein the plurality of transistors are of a same size.

14. The monolithically integrated circuital arrangement according to claim 1 , wherein at least one transistor of the plurality of transistors is of a size different from remaining transistors of the plurality of transistors.

15. The monolithically integrated circuital arrangement according to claim 1 , wherein:
the stack comprises a plurality of unit cells arranged in a parallel configuration, each unit cell being a reduced size replica of the stack, and
each gate capacitor of the N gate capacitors is distributed across the plurality of unit cells.

16. A monolithically integrated circuital arrangement comprising:
a stack of N transistors arranged in a cascode configuration, comprising an input transistor, M 1 , and N−1 cascode transistors, M 2 , M 3 , . . . , M N , comprising an output transistor, M N , N being an integer equal to or larger than two, the stack configured to operate between a supply voltage provided at a drain of the output transistor, M N , and a reference voltage provided at a source of the input transistor, M 1 ;
N−1 gate capacitors, C 2 , C 3 , . . . , C N−1 , each gate capacitor, C i , of the N−1 gate capacitors connected, at a first terminal of the each gate capacitor, C i , to a gate of a respective transistor, Mi, of the N−1 cascode transistors, wherein at least one gate capacitor, C k , of the N−1 gate capacitors associated to a transistor M k , is connected, at a second terminal of the at least one gate capacitor, C k , to a first terminal of a coupling gate capacitor, C k−1 , of the N−1 gate capacitors associated to a transistor M k−1 adjacent to the transistors M k , and remaining gate capacitors, C 2 , C 3 , . . . , C k−2 , C k−1 , C k+1 , . . . , C N , of the N−1 gate capacitors are connected, at a second terminal of each gate capacitor of the remaining gate capacitors, to the reference voltage.

17. A monolithically integrated circuital arrangement comprising:
a stack of a plurality of transistors arranged in a cascode configuration, comprising an input transistor and a plurality of cascode transistors;
a first gate capacitor connected between a gate of a first cascode transistor of the plurality of cascode transistors of the stack and a reference voltage, the first gate capacitor configured to provide a first RF voltage at the gate of the first cascode transistor by way of coupling of an RF voltage at a source of the first cascode transistor; and
a second gate capacitor connected between a gate of a second cascode transistor of the plurality of cascode transistor of the stack and the gate of the first cascode transistor, the second gate capacitor configured to couple the first RF voltage to the gate of the second cascode transistor and to further couple an RF voltage at a source of the second cascode transistor to the gate of the second cascode transistor to provide a second RF voltage at the gate of the second cascode transistor,
wherein the first RF voltage and the second RF voltage are based on a desired distribution of an RF voltage at an output of the stack across the plurality of transistors of the stack.

18. A method for realizing a monolithically integrated circuit comprising a

Assignees

• Psemi Corp

Inventors

• Adamski Jaroslaw

Classifications

• H03F1/223

  with MOSFET's · CPC title

• H03F3/211 Primary

  using a combination of several amplifiers (H03F3/60 takes precedence) · CPC title

• H03F3/3008

  Bifet SEPP output stages · CPC title

• H03F3/3037

  with asymmetric control, i.e. one control branch containing a supplementary phase inverting stage · CPC title

• H03F3/265

  with field-effect transistors only · CPC title