Butted Body Contact for SOI Transistor

Patent metadata

Field	Value
Publication number	US-2017141134-A1
Application number	US-201514945323-A
Country	US
Kind code	A1
Filing date	Nov 18, 2015
Priority date	Nov 18, 2015
Publication date	May 18, 2017
Grant date	—

Abstract

Systems, methods, and apparatus for an improved body tie construction that produces all the benefits of conventional body tie (H-gate, T-gate), without the limitations and degradations associated with those constructions are described. The improved body tie construction is configured to have a lower resistance body tie when the transistor is “off” (Vg approximately 0 volts). When the transistor is “on” (Vg>Vt), the resistance to the body tie is much higher, reducing the loss of performance associated with presence of body tie.

First claim

1 . A field-effect transistor (FET) comprising:
a drain region having a first conductivity type; a source region having the first conductivity type; a gate polysilicon structure defining a body region, the body region having a second conductivity type; at least one body contact region of the second conductivity type in contact with the source region and separate from the body region; and at least one body tab of the second conductivity type in contact with the body region and the at least one body contact region, configured to electrically connect the at least one body contact region to the body region.

2 . The field-effect transistor (FET) according to claim 1 , wherein the FET is a silicon-on-insulator (SOI) FET, fabricated using a silicon-on-insulator (SOI) technology.

3 . The field effect transistor (FET) according to claim 2 , wherein a silicon layer of the SOI FET is a thin-film silicon layer.

4 . The field-effect transistor (FET) according to claim 3 , wherein the at least one body contact region is fully contained within the source region.

5 . The field-effect transistor (FET) according to claim 3 , wherein the at least one body contact region abuts the source region.

6 . The field-effect transistor (FET) according to claim 3 , wherein the at least one body tab comprises two or more body tabs.

7 . The field-effect transistor (FET) according to claim 6 , wherein the two or more body tabs are symmetrically placed along a width of the body region.

8 . The field-effect transistor (FET) according to claim 3 , wherein the at least one body contact region comprises two or more body contact regions.

9 . The field-effect transistor (FET) according to claim 3 , further comprising at least one polysilicon tab configured to define the at least one body tab.

10 . The field-effect transistor (FET) according to claim 9 , wherein the at least one polysilicon tab and the gate polysilicon structure form a single polysilicon structure.

11 . The field-effect transistor (FET) according to claim 9 or claim 10 , wherein the at least one body tab provides a resistive conduction path between the body region and the body contact region with a resistance value which is a function of the ON or OFF state of the FET.

12 . The field-effect transistor (FET) according to claim 11 , wherein the resistance value can be adjusted via a length and a width of the at least one body tab.

13 . The field-effect transistor (FET) according to claim 11 , wherein the resistance value in the ON (conduction) state of the FET is substantially higher than the resistance value in the OFF (non-conduction) state of the FET.

14 . The field-effect transistor (FET) according to claim 11 , wherein the resistance value in the ON (conduction) state of the FET is at least ten times the resistance value in the OFF (non-conduction) state of the FET.

15 . The field-effect transistor (FET) according to claim 3 , further comprising a conductive layer atop the source region and the at least one body contact region.

16 . The field-effect transistor (FET) according to claim 15 , wherein the conductive layer is a silicide layer.

17 . The field-effect transistor (FET) according to claim 3 , further comprising a conductive contact atop a portion of the at least one body contact region.

18 . The field-effect transistor (FET) according to claim 3 , wherein the transistor is a metal-oxide-semiconductor field effect transistor (MOSFET).

19 . The field-effect transistor (FET) according to claim 18 , wherein the MOSFET is an N-type MOSFET with the drain region and the source region being N+ type regions, the body region and the at least one body tab being P− type regions, and the at least one body contact being a P+ type region.

20 . The field-effect transistor (FET) according to claim 18 , wherein the MOSFET is an P-type MOSFET with the drain region and the source region being P+ type regions, the body region and the at least one body tab being N− type regions, and the at least one body contact being a N+ type region.

21 . The field-effect transistor (FET) according to claim 2 , further comprising:
an insulating layer; and a silicon layer overlying the insulating layer, wherein the drain region, the source region, the body region, the at least one body contact region, and the body tab are formed in the silicon layer and extend through the silicon layer to reach the insulating layer.

22 . A multi-finger field-effect transistor (FET) comprising:
a first gate polysilicon structure defining a first body region, the first body region having a first conductivity type; a second gate polysilicon structure defining a second body region, the second body region having the first conductivity type; a first drain region adjacent to the first body region having a second conductivity type; a second drain region adjacent to the second body region having the second conductivity type; a common source region adjacent to the first and the second body regions having the second conductivity type; at least one body contact region of the first conductivity type formed within the common source region and separate from the first and the second body regions; at least one first body tab of the first conductivity type in contact with the first body region and the at least one body contact region, configured to electrically connect the at least one body contact region to the first body region, and at least one second body tab of the first conductivity type in contact with the second body region and the at least one body contact region, configured to electrically connect the at least one body contact region to the second body region.

23 . The multi-finger field-effect transistor (FET) according to claim 22 , wherein the FET is a silicon-on-insulator (SOI) FET, fabricated using a silicon-on-insulator (SOI) technology.

24 . The field effect transistor (FET) according to claim 23 , wherein a silicon layer of the SOI FET is a thin-film silicon layer.

25 . The multi-finger field-effect transistor (FET) according to claim 24 , wherein:
the at least one body contact region comprises a first body contact region and a second body contact region separate from the first body contact region; the at least one first body tab is in contact with the first body region and the first body contact region, and the at least one second body tab is in contact with the second body region and the second body contact region.

26 . The multi-finger field-effect transistor (FET) according to claim 24 , further comprising at least one first polysilicon tab configured to define the at least one first body tab, and at least one second polysilicon tab configured to define the at least one second body tab.

27 . The multi-finger field-effect transistor (FET) according to claim 26 , wherein the at least one first polysilicon tab and the at least one second polysilicon tab are joint and form with the first gate polysilicon structure and the second gate polysilicon structure a single polysilicon structure.

28 . The multi-finger field-effect transistor (FET) according to claim 24 , further comprising an isolation region having the first conductivity type which isolates the at least one body contact region from the common source region.

29 . The multi-finger field-effect transistor (FET) according to claim 28 , fu

Assignees

• Peregrine Semiconductor Corp

Inventors

• Willard Simon Edward

Classifications

• H01L27/1218

  Electricity · mapped topic

• H01L29/4916

  Electricity · mapped topic

• H01L27/1251 Primary

  Electricity · mapped topic

• H01L29/78603

  Electricity · mapped topic

• H01L29/458

  Electricity · mapped topic