High-frequency filter and electronic device

US9947979B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9947979-B2
Application numberUS-201615393301-A
CountryUS
Kind codeB2
Filing dateDec 29, 2016
Priority dateFeb 1, 2013
Publication dateApr 17, 2018
Grant dateApr 17, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A flat cable high-frequency filter includes a dielectric substrate extending in a transmission direction of a high-frequency signal. The dielectric substrate includes dielectric layers stacked on each other. Elongated conductor patterns are provided on a flat surface of one dielectric layer which faces another dielectric layer. The conductor patterns are as wide as possible in the dielectric substrate in accordance with a desired inductance. A capacitive coupling conductor pattern opposes one conductor pattern by a predetermined area with a dielectric layer therebetween. By using a connecting conductor, the capacitive coupling conductor pattern is connected to the conductor pattern which does not oppose the capacitive coupling conductor pattern.

First claim

Opening claim text (preview).

What is claimed is: 1. A high-frequency filter connected between a first circuit element including an antenna and a second circuit element, the high-frequency filter comprising: a dielectric substrate that includes a flat film; a plurality of conductor patterns that are not connected to each other and include a gap provided between opposing end portions of the plurality of conductor patterns; and a capacitive coupling conductor pattern that is superposed on the plurality of conductor patterns in a thickness direction of the dielectric substrate through the dielectric substrate and is configured to capacitively couple the plurality of conductor patterns, wherein the plurality of conductor patterns define inductors; the capacitive coupling conductor pattern defines a capacitor; and a region of the dielectric substrate in which the capacitive coupling conductor pattern is located is provided at a position closer to the second circuit element than to the first circuit element in the dielectric substrate. 2. The high-frequency filter according to claim 1 , further comprising a linear conductor provided in the dielectric substrate between the first circuit element and the region in which the capacitive coupling conductor pattern is located. 3. The high-frequency filter according to claim 1 , wherein, in the dielectric substrate, a bent portion is located at a position other than the region in which the capacitive coupling conductor pattern is located. 4. The high-frequency filter according to claim 1 , wherein the first circuit element and the second circuit element are located at different positions in a height direction from each other; the first circuit element is connected to a first surface of the dielectric substrate; and the second circuit element is connected to a second surface of the dielectric substrate. 5. The high-frequency filter according to claim 1 , wherein the first circuit element and the second circuit element are connected through a connector provided on a surface of the dielectric substrate. 6. The high-frequency filter according to claim 1 , wherein the second circuit element includes a substrate on which at least one of an integrated circuit (IC) chip and a mount component is mounted. 7. The high-frequency filter according to claim 1 , wherein the dielectric substrate has a dielectric loss tangent equal to or smaller than about 0.005. 8. The high-frequency filter according to claim 7 , wherein the dielectric substrate is made of a liquid crystal polymer. 9. The high-frequency filter according to claim 1 , wherein the capacitive coupling conductor pattern includes: a flat conductor pattern which opposes a certain one of the plurality of conductor patterns with a dielectric layer of the dielectric substrate therebetween; and a flat region of the certain one of the plurality of conductor patterns which opposes the flat conductor pattern. 10. The high-frequency filter according to claim 9 , wherein a width of a conductor pattern which opposes the capacitive coupling conductor pattern is the same or substantially the same as a width of a conductor pattern which does not oppose the capacitive coupling conductor pattern. 11. The high-frequency filter according to claim 10 , wherein the width of the conductor patterns which opposes the capacitive coupling conductor pattern and the width of a conductor pattern which does not oppose the capacitive coupling conductor pattern are the same or substantially the same as a width of the dielectric substrate. 12. An electronic device comprising: the high-frequency filter according to claim 1 ; and a plurality of mount circuit members; wherein the plurality of mount circuit members are connected to each other by the high-frequency filter. 13. The electronic device according to claim 12 , wherein the high-frequency filter is disposed with a predetermined gap from each of the plurality of mount circuit members. 14. An electronic device comprising: a first circuit element including an antenna; a second circuit element; and a high-frequency filter connected between the first circuit element and the second circuit element, the high-frequency filter comprising: a dielectric substrate that includes a flat film; a plurality of conductor patterns that are not connected to each other and include a gap provided between opposing end portions of the plurality of conductor patterns; and a capacitive coupling conductor pattern that is superposed on the plurality of conductor patterns in a thickness direction of the dielectric substrate through the dielectric substrate and is configured to capacitively couple the plurality of conductor patterns, wherein: the plurality of conductor patterns define inductors; the capacitive coupling conductor pattern defines a capacitor; and a region of the dielectric substrate in which the capacitive coupling conductor pattern is located is provided at a position closer to the second circuit element than to the first circuit element in the dielectric substrate. 15. The electronic device according to claim 14 , further comprising a linear conductor provided in the dielectric substrate between the first circuit element and the region in which the capacitive coupling conductor pattern is located. 16. The electronic device according to claim 14 , wherein, in the dielectric substrate, a bent portion is located at a position other than the region in which the capacitive coupling conductor pattern is located. 17. The electronic device according to claim 14 , wherein the first circuit element and the second circuit element are located at different positions in a height direction from each other; the first circuit element is connected to a first surface of the dielectric substrate; and the second circuit element is connected to a second surface of the dielectric substrate. 18. The electronic device according to claim 14 , wherein the first circuit element and the second circuit element are connected through a connector provided on a surface of the dielectric substrate. 19. The electronic device according to claim 14 , wherein the second circuit element includes a substrate on which at least one of an integrated circuit (IC) chip and a mount component is mounted.

Assignees

Inventors

Classifications

  • H01P1/2013Primary

    Coplanar line filters · CPC title

  • Printed circuits associated with mounted high frequency components · CPC title

  • Multilayer filters · CPC title

  • Filters for transverse electromagnetic waves (H01P1/212, H01P1/213, H01P1/215, H01P1/219 take precedence) · CPC title

  • Stacked transmission lines · CPC title

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What does patent US9947979B2 cover?
A flat cable high-frequency filter includes a dielectric substrate extending in a transmission direction of a high-frequency signal. The dielectric substrate includes dielectric layers stacked on each other. Elongated conductor patterns are provided on a flat surface of one dielectric layer which faces another dielectric layer. The conductor patterns are as wide as possible in the dielectric su…
Who is the assignee on this patent?
Murata Manufacturing Co
What technology area does this patent fall under?
Primary CPC classification H01P1/2013. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 17 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).