Low noise device and method of forming the same

Patent metadata

Field	Value
Publication number	US-9947701-B2
Application number	US-201715428356-A
Country	US
Kind code	B2
Filing date	Feb 9, 2017
Priority date	May 31, 2016
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

A low noise device includes an isolation feature in a substrate. The low noise device further includes a gate stack over a channel in the substrate. The gate stack includes a gate dielectric layer extending over a portion of the isolation feature, and a gate electrode over the gate dielectric layer. The low noise device further includes a charge trapping reducing structure adjacent to the isolation feature. The charge trapping reducing structure is configured to reduce a number of charge carriers adjacent an interface between the isolation feature and the channel.

First claim

What is claimed is:

1. A low noise device comprising:
an isolation feature in a substrate;
a gate stack over a channel in the substrate, wherein the gate stack comprises:
a gate dielectric layer extending over a portion of the isolation feature, and
a gate electrode over the gate dielectric layer; and
a charge trapping reducing structure adjacent to the isolation feature, wherein the charge trapping reducing structure directly contacts an uppermost surface of the substrate, and the charge trapping reducing structure is configured to reduce a number of charge carriers adjacent an interface between the isolation feature and the channel.

2. The low noise device of claim 1 , wherein the charge trapping reducing structure comprises an isolation feature overhang extending over a portion of the channel.

3. The low noise device of claim 1 , wherein the charge trapping reducing structure comprises a dielectric material extending over a portion of the channel adjacent to the isolation feature, and the dielectric material is different from the gate dielectric layer.

4. The low noise device of claim 3 , wherein the dielectric material extends over the channel for a distance of at least about 5 nanometers (nm).

5. The low noise device of claim 3 , wherein the charge trapping reducing structure further comprises an implant region.

6. The low noise device of claim 3 , wherein the charge trapping reducing structure further comprises a doped contact in the substrate on an opposite side of the isolation feature from the channel.

7. The low noise device of claim 1 , wherein the charge trapping reducing structure comprises an implant region at an interface between the isolation feature and the channel.

8. The low noise device of claim 7 , wherein the implant region comprises a non-dopant material.

9. The low noise device of claim 1 , wherein the charge trapping reducing structure is a doped contact in the substrate on an opposite side of the isolation feature from the channel.

10. A low noise device comprising:
an isolation feature in a substrate;
a gate stack over a channel in the substrate, wherein the isolation feature contacts the channel; and
a doped contact in the substrate on an opposite side of the isolation feature from the channel, wherein the doped contact defines a varactor, and the doped contact is in contact with the isolation feature, and an edge of the gate stack is spaced from an edge of the isolation feature adjacent to the doped contact by a distance ranging from a minimum spacing distance to about 0.3 microns (μm).

11. The low noise device of claim 10 , wherein the gate stack extends over the isolation feature.

12. The low noise device of claim 10 , further comprising an implant region at an interface between the isolation feature and the channel, wherein the implant region comprises a non-dopant material.

13. The low noise device of claim 10 , wherein a dopant concentration of the doped contact is at least about 1×10 11 ions/cm 3 .

14. The low noise device of claim 10 , wherein the isolation feature includes a first section in the substrate, and a second section over the channel.

15. The low noise device of claim 10 , further comprising an implant region at an interface between the isolation feature and the channel.

16. A low noise device comprising:
an isolation feature in a substrate;
a gate stack over a channel in the substrate, wherein the isolation feature contacts the channel; and
an implant region at an interface between the isolation feature and the channel, wherein the implant region comprises a non-dopant material.

17. The low noise device of claim 16 , wherein the non-dopant material comprises a fluorine-containing material.

18. The low noise device of claim 16 , wherein a concentration of the non-dopant material is at least about 1×10 12 ions/cm 3 .

19. The low noise device of claim 16 , wherein the isolation feature includes a first section in the substrate, and a second section over the channel.

20. The low noise device of claim 16 , further comprising a doped contact in the substrate on an opposite side of the isolation feature from the channel.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liang Victor Chiang
• Tsai Fu-Huan
• Kuo Fang-Ting
• Ho Meng-Chang
• Wei Yu-Lin
• Huang Chi-Feng

Classifications

• H01L27/14603 Primary

  Electricity · mapped topic

• H01L27/0733

  Electricity · mapped topic

• H01L29/93

  Electricity · mapped topic

• H10D84/813

  Combinations of field-effect devices and capacitor only · CPC title

• H10D1/64 Primary

  Variable-capacitance diodes, e.g. varactors · CPC title