Three-dimensional semiconductor device

Patent metadata

Field	Value
Publication number	US-9947684-B2
Application number	US-201615241781-A
Country	US
Kind code	B2
Filing date	Aug 19, 2016
Priority date	Dec 17, 2015
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

A semiconductor device includes a substrate including a cell region and a connection region. A stack is disposed on the substrate. A vertical channel structure penetrates the stack in the cell region. The stack includes electrode patterns and insulating patterns which are alternatingly and repeatedly stacked on the substrate. Each of the electrode patterns may extend in a first direction and include a pad portion. The pad portion is positioned in the connection region. The pad portion includes a first sidewall and a second sidewall that extend in the first direction on opposite sides of the pad portion. The first sidewall has a recessed portion that is recessed in a second direction crossing the first direction toward the second sidewall.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate comprising a cell region and a connection region;
a stack disposed on the substrate;
a vertical channel structure penetrating the stack in the cell region,
wherein the stack comprises electrode patterns and insulating patterns, wherein the electrode patterns and the insulating patterns are alternatingly and repeatedly stacked on the substrate,
wherein each of the electrode patterns extends in a first direction and comprises a pad portion, and wherein the pad portion is positioned in the connection region and is exposed by another of the electrode patterns thereon,
wherein the pad portion comprises a first sidewall and a second sidewall that extend in the first direction on opposite sides of the pad portion, and
wherein the first sidewall has a recessed portion that is recessed in a second direction crossing the first direction toward the second sidewall;
a first portion extending from the recessed portion to the second sidewall in the second direction; and
a second portion extending from a portion of the first sidewall adjacent to the recessed portion to the second sidewall in the second direction,
wherein a width of the first portion along the second direction is smaller than that of the second portion.

2. The device of claim 1 , further comprising dummy pillars penetrating the stack in the connection region,
wherein each of the dummy pillars penetrates the second portion of the pad portion.

3. The device of claim 1 , wherein the second sidewall has an additional recessed portion that is recessed in the second direction toward the first sidewall.

4. The device of claim 3 , wherein the additional recessed portion is included in the first portion.

5. The device of claim 1 , wherein the recessed portion is formed in a sidewall of the stack, and wherein the recessed portion extends along a direction perpendicular to the substrate.

6. The device of claim 5 , wherein the recessed portion is a concavely recessed trench-shaped region.

7. The device of claim 1 , further comprising dummy pillars penetrating the stack in the connection region,
wherein, when viewed in a plan view, the dummy pillars are overlapped with a boundary between adjacent pad portions.

8. The device of claim 7 , wherein, when viewed in the plan view, the recessed portion is spaced apart from the boundary between the adjacent pad portions.

9. A semiconductor device, comprising:
a substrate comprising a cell region and a connection region;
a stack disposed on the substrate and extending in a first direction; and
a vertical channel structure penetrating the stack in the cell region,
wherein the stack comprises electrode patterns and insulating patterns, wherein the electrode patterns and the insulating patterns are alternatingly and repeatedly stacked on the substrate,
wherein the stack has a staircase structure in the connection region,
wherein the staircase structure comprises a sidewall extending in the first direction,
wherein the sidewall comprises non-recessed portions and recessed portions,
wherein the recessed portions are laterally recessed toward the stack,
wherein each of the recessed portions extends in a direction perpendicular to the first direction, and
wherein each of the recessed portions is a concavely recessed trench-shaped region.

10. The device of claim 9 , wherein the non-recessed portions and the recessed portions are alternatingly arranged in the first direction.

11. The device of claim 9 , wherein the staircase structure includes a plurality of staircase sidewalls, each of which extends in a second direction crossing the first direction, and wherein heights of the staircase sidewalls decrease along the first direction, and
wherein the staircase sidewalls are connected to the non-recessed portions of the sidewall.

12. The device of claim 11 , further comprising dummy pillars penetrating the stack in the connection region,
wherein, when viewed in a plan view, the dummy pillars are overlapped with the staircase sidewalls.

13. The device of claim 12 , wherein, when viewed in the plan view, a first minimum of distances from each of the dummy pillars to the recessed portions is greater than or equal to a second minimum of distances from each of the dummy pillars to the non-recessed portions.

14. A semiconductor device, comprising:
a substrate comprising a cell region and a connection region;
a stack vertically extending from the substrate, wherein the stack comprises a plurality of electrode patterns and a plurality of insulating patterns alternatingly and repeatedly stacked on the substrate; and
a plurality of dummy pillars penetrating the plurality of electrode patterns and the plurality of insulating patterns in the connection region,
wherein each of the plurality of electrode patterns comprises a pad portion in the connection region,
wherein the pad portion comprises a first portion comprising a non-recessed portion along a sidewall of the pad portion and a second portion comprising a recessed portion along the sidewall of the pad portion,
wherein the dummy pillars are aligned with the non-recessed portion of the pad portion along a direction perpendicular to the sidewall of the pad portion when the dummy pillars and the pad portion are viewed in a plan view, and
wherein the recessed portion is a concavely recessed trench-shaped region.

15. The semiconductor device of claim 14 , further comprising a vertical channel structure penetrating the stack in the cell region.

16. The semiconductor device of claim 14 , wherein the recessed portion comprises a plurality of recessed portions arranged along the sidewall of the pad portion.

17. The semiconductor device of claim 16 , wherein the recessed portions are substantially evenly spaced, and wherein each of the recessed portions are separated from adjacent recessed portions by at least one non-recessed portion.

Assignees

• Park Joyoung
• Kwon Yong Hyun
• Kim Jeongsoo
• Lee Seok Won
• Park Jinwoo
• Kwon Oik
• Chung Seungpil
• Samsung Electronics Co Ltd

Inventors

• Park Joyoung
• Kwon Yong-Hyun
• Kim Jeongsoo
• Lee Seok-Won
• Park Jinwoo
• Kwon Oik
• Chung Seungpil

Classifications

• H01L27/11568

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H10B43/50

  characterised by the boundary region between the core and peripheral circuit regions · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title