Semiconductor package

Patent metadata

Field	Value
Publication number	US-9947644-B2
Application number	US-201615268658-A
Country	US
Kind code	B2
Filing date	Sep 19, 2016
Priority date	Dec 15, 2015
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

A semiconductor package is provided. The semiconductor package may include a plurality of memory chips, which are mounted on a top surface of a package substrate, and a plurality of controller chips, which are vertically stacked on at least one of top and bottom surfaces of the package substrate.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a package substrate including a first surface and a second surface opposite to each other;
memory chips on the first surface of the package substrate; and
controller chips vertically stacked on at least one of the first and second surfaces of the package substrate and electrically connected to the memory chips and the package substrate.

2. The semiconductor package as claimed in claim 1 , wherein the controller chips are mounted on the first surface of the package substrate and are spaced apart from the memory chips in a horizontal direction.

3. The semiconductor package as claimed in claim 1 , wherein the first surface of the package substrate has a recessed region on which the controller chips are mounted.

4. The semiconductor package as claimed in claim 1 , wherein the memory chips are mounted on a center region of the first surface of the package substrate, and
the controller chips are mounted on an edge region of the first surface of the package substrate.

5. The semiconductor package as claimed in claim 1 , wherein the controller chips are mounted on the second surface of the package substrate.

6. The semiconductor package as claimed in claim 5 , further comprising outer terminals provided on the second surface of the package substrate,
wherein the controller chips are on a center region of the second surface of the package substrate, and
the outer terminals are on an edge region of the second surface of the package substrate.

7. The semiconductor package as claimed in claim 1 , wherein the second surface of the package substrate has a recessed region on which the controller chips are mounted.

8. The semiconductor package as claimed in claim 7 , wherein the recessed region is in a center region of the second surface of the package substrate.

9. The semiconductor package as claimed in claim 1 , wherein the memory chips include chip pads, respectively, which are provided at edge regions thereof, and
at least some of the memory chips are respectively shifted in a direction from an underlying one of the memory chips such that the chip pad of the underlying one of the memory chips is exposed.

10. The semiconductor package as claimed in claim 9 , wherein the memory chips include:
first memory chips constituting a lower group; and
second memory chips provided on the lower group to constitute an upper group,
wherein:
upper ones of the first memory chips are respectively shifted in a first direction from an underlying one of the first memory chips,
upper ones of the second memory chips are respectively shifted in the first direction from an underlying one of the second memory chips, and
the lowermost one of the second memory chips of the upper group is shifted, in a second direction opposite to the first direction, from the uppermost one of the first memory chips of the lower group.

11. The semiconductor package as claimed in claim 10 , further comprising a connector electrically connecting the memory chips, the controller chips, and the package substrate to each other.

12. The semiconductor package as claimed in claim 11 , wherein the connector includes:
a chip-to-chip connector electrically connecting at least two of the first memory chips to each other, electrically connecting at least two of the second memory chips to each other, or electrically connecting the upper group to the lower group;
a chip-to-substrate connector electrically connecting at least one of the first memory chips, at least one of the second memory chips, or at least one of the controller chips to the package substrate; and
a structure-to-structure connector electrically connecting at least one of the first and second memory chips to at least one of the controller chips.

13. The semiconductor package as claimed in claim 9 , wherein the memory chips include:
first memory chips constituting a lower group; and
second memory chips provided on the lower group to constitute an upper group,
wherein:
upper ones of the first memory chips are respectively shifted in a first direction from an underlying one of the first memory chips, and
upper ones of the second memory chips are respectively shifted, in a second direction opposite to the first direction, from an underlying one of the second memory chips.

14. The semiconductor package as claimed in claim 13 , further comprising a connector electrically connecting at least one of the first memory chips, at least one of the second memory chips, or at least one of the controller chips to the package substrate.

15. A semiconductor package, comprising:
a package substrate including a first surface and a second surface opposite to each other;
a memory chip structure including memory chips vertically stacked on the first surface of the package substrate; and
a controller chip structure on the second surface of the package substrate and including at least two controller chips vertically stacked on the package substrate,
wherein the memory chip structure further includes:
first bonding wires, each of which is provided to electrically connect at least two of the memory chips to each other; and
second bonding wires, each of which is provided to electrically connect at least one of the memory chips to the package substrate,
wherein the controller chip structure further includes third bonding wires, each of which is provided to electrically connect one of the controller chips to the package substrate.

16. A semiconductor device, comprising:
first semiconductor chips arranged in a first stack on a substrate, the first semiconductor chips being memory controllers; and
second semiconductor chips arranged in a second stack on the substrate, the second semiconductor chips being memory chips controlled based on signals from the first semiconductor chips, the second semiconductor chips including a first set of second semiconductor chips controlled by a first one of the first semiconductor chips, and including a second set of second semiconductor chips controlled by a second one of the first semiconductor chips.

17. The semiconductor device as claimed in claim 16 , wherein each of the first and second semiconductor chips has a wire bonded connection.

18. The semiconductor device as claimed in claim 16 , wherein the first semiconductor chips are each identical to one another and the second semiconductor chips are each identical to one another, and the first semiconductor chips are different from the second semiconductor chips.

19. The semiconductor device as claimed in claim 16 , wherein the first stack is offset on the substrate laterally from the second stack, and the substrate under the first stack is thinner than the substrate under the second stack.

20. The semiconductor device as claimed in claim 16 , wherein the second stack is on an opposite side of the substrate from the first stack, and the second stack is in a recess in the substrate, portions of the substrate that are spaced apart laterally from the second stack being thicker than the substrate at the recess.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hong Jinhee
• PARK Wansoo
• Park Chul

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title