Multi-chip package having a logic chip disposed in a package substrate opening and connecting to an interposer

Patent metadata

Field	Value
Publication number	US-9299685-B2
Application number	US-201414451520-A
Country	US
Kind code	B2
Filing date	Aug 5, 2014
Priority date	Aug 5, 2013
Publication date	Mar 29, 2016
Grant date	Mar 29, 2016

Abstract

A multi-chip package may include a package substrate, a connecting substrate, a plurality of semiconductor chips and a logic chip. The package substrate may have an opening. The connecting substrate may be arranged on an upper surface of the package substrate. The semiconductor chips may be stacked on an upper surface of the connecting substrate. The semiconductor chips may be electrically connected with the connecting substrate. The logic chip may be arranged in the opening. The logic chip may be electrically connected between the connecting substrate and the package substrate. Thus, the logic chip may not act as to increase a width of the multi-chip package.

First claim

What is claimed is:

1. A multi-chip package comprising:
a package substrate including an opening therein;
an interposer disposed on the package substrate to cover the opening;
a stack of semiconductor chips disposed on a first surface of the interposer;
a logic chip disposed in the opening and on a second surface of the interposer opposite the first surface; and
a first logic pad on a surface of the logic chip and electrically connected to a second pad of the interposer located at the opening, the second pad electrically connected to the stack of semiconductor chips,
wherein the logic chip electrically connects to the stack of semiconductor chips through the interposer and also includes direct electrical connections to the package substrate that do not pass through the interposer.

2. The multi-chip package of claim 1 , wherein the stack of semiconductor chips comprises a first group of semiconductor chips and a second group of semiconductor chips; wherein:
the first group of semiconductor chips is directly electrically connected to the interposer without being connected through the package substrate; and
the second group of semiconductor chips is directly electrically connected to the package substrate.

3. The multi-chip package of claim 1 , further comprising:
a pad on a bottom surface of the interposer and directly electrically connected to the logic chip; and
a pad on a top surface of the interposer and directly electrically connected to at least a first semiconductor chip of the stack of semiconductor chips.

4. The multi-chip package of claim 3 , further comprising:
a pad on a top surface of the interposer that is directly electrically connected to the package substrate.

5. The multi-chip package of claim 3 , wherein the second pad located at the opening is the same pad as the pad on the bottom surface of the interposer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Kil-Soo

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title