Multilayer ceramic capacitor, multilayer ceramic capacitor series including the same, and multilayer ceramic capacitor mount body including the same

Patent metadata

Field	Value
Publication number	US-9947476-B2
Application number	US-201715656114-A
Country	US
Kind code	B2
Filing date	Jul 21, 2017
Priority date	Aug 13, 2014
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

A body of a multilayer ceramic capacitor includes an inner layer portion and first and second outer layer portions sandwiching the inner layer portion therebetween. The inner layer portion includes an area extending from a conductive layer positioned closest to a first main surface to a conductive layer positioned closest to a second main surface in the stacking direction. The height of the body is smaller than the width of the body. The height of the inner layer portion is smaller than the width of the inner layer portion. The first outer layer portion includes a dielectric layer positioned closest to the first main surface. The second outer layer portion includes a dielectric layer positioned closest to the second main surface, and is thicker than the first outer layer portion. The total height of the first and second outer layer portions is smaller than the height of the inner layer portion.

First claim

What is claimed is:

1. A multilayer ceramic capacitor comprising:
a body that includes a plurality of dielectric layers and a plurality of conductive layers stacked on each other in a stacking direction and that includes first and second main surfaces opposing each other in the stacking direction, first and second end surfaces opposing each other in a length direction and connecting the first and second main surfaces, and first and second side surfaces opposing each other in a width direction and connecting the first and second main surfaces and the first and second end surfaces; and
first and second outer electrodes that are disposed on portions of a surface of the body; wherein
the body includes a first outer layer portion including a first of the plurality of dielectric layers defining the first main surface, a second outer layer portion including a second of the plurality of dielectric layers defining the second main surface, and an inner layer portion adjacent to both of the first outer layer portion and the second outer layer portion, the inner layer portion includes a portion extending from a first outermost conductive layer positioned closest to the first main surface among the plurality of conductive layers through a second outermost conductive layer positioned closest to the second main surface among the plurality of conductive layers in the stacking direction;
a dimension of the body in the stacking direction is smaller than a dimension of the body in the width direction;
the second outer layer portion includes an outer portion including the second main surface and an inner portion adjacent to both of the outer portion and the inner layer portion; and
the outer portion includes a boundary region adjacent to the inner portion which has a larger Si content compared to a central region of the outer portion.

2. The multilayer ceramic capacitor according to claim 1 , wherein a dimension of the second outer layer portion in the stacking direction is greater than a dimension of the first outer layer portion in the stacking direction.

3. The multilayer ceramic capacitor according to claim 1 , wherein a total dimension of the first outer layer portion and the second outer layer portion in the stacking direction is smaller than a dimension of the inner layer portion in the stacking direction.

4. The multilayer ceramic capacitor according to claim 1 , wherein a dimension of the inner layer portion in the stacking direction is smaller than a dimension of a portion of the inner layer portion where the plurality of conductive layers are stacked in the width direction.

5. The multilayer ceramic capacitor according to claim 1 , wherein a dimension of the outer portion in the stacking direction is about 30 μm or greater.

6. The multilayer ceramic capacitor according to claim 1 , wherein a dimension of the inner portion in the stacking direction is about 20 μm or greater.

7. The multilayer ceramic capacitor according to claim 1 , wherein the body includes side gaps between each of the first and second side surfaces and the inner layer portion, and a maximum dimension or an average dimension of the side gaps in the width direction is greater than about 30 μm and less than about 90 μm.

8. The multilayer ceramic capacitor according to claim 1 , wherein a composition ratio of Si relative to Ti of the outer portion is higher than that of one of the plurality of dielectric layers included in the inner layer portion and that of the inner portion.

9. The multilayer ceramic capacitor according to claim 1 , wherein, when viewed from the width direction, the boundary region includes a portion that inclines toward the first main surface as the boundary region gets closer to one of the first and second end surfaces.

10. The multilayer ceramic capacitor according to claim 1 , wherein the dimension of the body in the width direction is greater than about 0.9 mm and the dimension of the body in the stacking direction is smaller than about 0.9 mm.

11. The multilayer ceramic capacitor according to claim 1 , wherein a dimension of the second outer layer portion in the stacking direction is about 90 μm or greater and is equal to or smaller than about ¼ of a dimension of the inner layer portion in the stacking direction.

12. The multilayer ceramic capacitor according to claim 1 , wherein the body includes side gaps between each of the first and second side surfaces and the inner layer portion, and an average dimension of the side gaps in the width direction is greater than a dimension of the first outer layer portion in the stacking direction.

13. The multilayer ceramic capacitor according to claim 1 , wherein a difference between a dimension of the second outer layer portion in the stacking direction and a dimension of the first outer layer portion in the stacking direction is about 10 μm or greater.

14. The multilayer ceramic capacitor according to claim 1 , wherein a dimension of the first outer layer portion in the stacking direction is about 10 μm or greater, and a dimension of the second outer layer portion in the stacking direction is about 90 μm or greater.

15. The multilayer ceramic capacitor according to claim 1 , wherein the outer portion includes a surface region adjacent to the second main surface which has a larger Si content compared to the central region of the outer portion.

16. The multilayer ceramic capacitor according to claim 1 , wherein each of the plurality of dielectric layers includes at least one of Dy, Gd, Y, and La.

17. The multilayer ceramic capacitor according to claim 1 , wherein a molar ratio of a rare earth element to Ti of dielectric layers of the plurality of dielectric layers included in the inner layer portion and a dielectric layer of the plurality of dielectric layers included in the inner portion is about 0.3 mol % or greater, and a molar ratio of a rare earth element to Ti of a dielectric layer of the plurality of dielectric layers included in the outer layer portion is less than about 0.3 mol %.

18. The multilayer ceramic capacitor according to claim 1 , wherein a Mn compound is included in the plurality of dielectric layers, a molar ratio of the Mn compound to Ti of dielectric layers of the plurality of dielectric layers included in the inner layer portion, the first of the plurality of dielectric layers, and a dielectric layer of the plurality of dielectric layers included in the inner portion is higher than that of a dielectric layer of the plurality of dielectric layers included in the outer portion.

19. The multilayer ceramic capacitor according to claim 18 , wherein the molar ratio of the Mn compound to Ti of the dielectric layers of the plurality of dielectric layers included in the inner layer portion, the first of the plurality of dielectric layers, and the dielectric layer of the plurality of dielectric layers included in the inner portion is about 0.08 mol % or greater, and the molar ratio of the Mn compound to Ti of the dielectric layer of the plurality of dielectric layers included in the outer portion is less than about 0.08 mol %.

20. A multilayer ceramic capacitor mount body comprising:
the multilayer ceramic capacitor according to claim 1 ; and
a substrate on which the multilayer ceramic capacitor is mounted; wherein
the second main surface of the multilayer ceramic capacitor faces the substrate.

21. The multilayer ceramic capacitor mount body according to claim 20 , wherein
the substrate includes two lands on a surface of the substrate, the two lands being electrically c

Assignees

• Murata Manufacturing Co

Inventors

• Kitano Shota
• Katsuyama Takanobu
• Sugita Hiroaki

Classifications

• H01G4/38

  Multiple capacitors, i.e. structural combinations of fixed capacitors · CPC title

• H01G4/12

  Ceramic dielectrics {(H01G4/085 takes precedence)} · CPC title

• H01G4/012

  Form of non-self-supporting electrodes · CPC title

• H01G4/30 Primary

  Stacked capacitors (H01G4/33 takes precedence) · CPC title

• H01G4/1209

  characterised by the ceramic dielectric material (H01G4/1272, H01G4/1281 take precedence) · CPC title