Device and methods for writing and erasing analog information in small memory units via voltage pulses

Patent metadata

Field	Value
Publication number	US-9947379-B1
Application number	US-201615287552-A
Country	US
Kind code	B1
Filing date	Oct 6, 2016
Priority date	Oct 6, 2016
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

Devices and methods for non-volatile analog data storage are described herein. In an exemplary embodiment, an analog memory device comprises a potential-carrier source layer, a barrier layer deposited on the source layer, and at least two storage layers deposited on the barrier layer. The memory device can be prepared to write and read data via application of a biasing voltage between the source layer and the storage layers, wherein the biasing voltage causes potential-carriers to migrate into the storage layers. After initialization, data can be written to the memory device by application of a voltage pulse between two storage layers that causes potential-carriers to migrate from one storage layer to another. A difference in concentration of potential carriers caused by migration of potential-carriers between the storage layers results in a voltage that can be measured in order to read the written data.

First claim

What is claimed is:

1. An analog memory system, comprising:
a barrier layer;
a first potential-carrier storage layer deposited on the barrier layer;
a second potential-carrier storage layer deposited on the barrier layer, the second storage layer physically separate from the first storage layer, and wherein responsive to a voltage pulse being applied between the first storage layer and the second storage layer, potential-carrier ions migrate from the first storage layer to the second storage layer by way of the barrier layer; and
a potential-carrier source layer, the barrier layer deposited on the source layer, wherein responsive to a voltage being applied between the source layer and the respective first and second storage layers, potential-carrier ions migrate from the source layer to the first and second storage layers.

2. The analog memory system of claim 1 , wherein the ions are lithium ions.

3. The analog memory system of claim 1 , wherein the source layer comprises lithium cobalt oxide (LiCoO 2 ).

4. The analog memory system of claim 3 , wherein the LiCoO 2 source layer has a thickness of between 250 and 350 nanometers.

5. The analog memory system of claim 3 , further comprising a conducting layer, wherein the LiCoO 2 source layer is deposited on the conducting layer, and wherein responsive to a voltage being applied between the conducting layer and the respective first and second storage layers, potential-carrier ions migrate from the source layer to the first and second storage layers.

6. The analog memory system of claim 1 , wherein the barrier layer comprises lithium-phosphor oxy-nitride (LiPON).

7. The analog memory system of claim 6 , wherein the LiPON barrier layer has a thickness of between 350 and 450 nanometers.

8. The analog memory system of claim 1 , wherein the first and second storage layers comprise respective first and second silicon layers.

9. The analog memory system of claim 8 , the first and second storage layers further comprising respective first and second conducting layers, the first and second conducting layers deposited on the first and second silicon layers, respectively, wherein the ions migrate from the first silicon layer to the second silicon layer responsive to the voltage pulse being applied between the first and second conducting layers.

10. A method for using analog memory, comprising:
writing data to a memory device, the memory device comprising:
a barrier layer;
a first storage layer deposited on the barrier layer; and
a second storage layer deposited on the barrier layer, the second storage layer physically separate from the first storage layer, and wherein responsive to a voltage pulse being applied between the first storage layer and the second storage layer, potential-carrier ions migrate from the first storage layer to the second storage layer by way of the barrier layer;
a potential-carrier source layer, the barrier layer deposited on the source layer, wherein responsive to a voltage being applied between the source layer and the respective first and second storage layers, potential-carrier ions migrate from the source layer to the first and second storage layers; and

reading the data from the memory device.

11. The method of claim 10 , wherein writing the data to the memory device comprises applying a voltage pulse between the first storage layer and the second storage layer, wherein the voltage pulse causes ions to move from the first storage layer to the second storage layer.

12. The method of claim 11 , wherein the first storage layer and the second storage layer comprise silicon, wherein responsive to applying the voltage pulse between the first storage layer and the second storage layer, lithium ions move from the first storage layers to the second storage layer.

13. The method of claim 10 , wherein reading the data from the memory device comprises measuring a voltage between the first storage layer and the second storage layer, the voltage being based upon a number of ions present in the first storage layer relative to a number of ions present in the second storage layer.

14. A memory device, comprising:
a lithium-phosphor oxy-nitride (LiPON) layer;
a first memory component comprising:
a first silicon layer deposited on the LiPON layer; and
a first conducting layer deposited on the first silicon layer; and

a second memory component comprising:
a second silicon layer deposited on the LiPON layer, the second silicon layer physically separate from the first silicon layer; and
a second conducting layer deposited on the second silicon layer; and

wherein responsive to a voltage being applied between the first conducting layer and the second conducting layer, lithium ions migrate from the first silicon layer to the second silicon layer by way of the LiPON layer.

15. The memory device of claim 14 , wherein the LiPON layer has a thickness of between 350 and 450 nanometers.

16. The memory device of claim 14 , the first and second silicon layers having respective thicknesses of between 30 and 70 nanometers.

17. The memory device of claim 14 , further comprising
a third conducting layer; and
a lithium cobalt oxide (LiCoO 2 ) layer deposited on the third conducting layer, the LiPON layer deposited on the LiCoO 2 layer, wherein responsive to a voltage being applied between the third conducting layer and the first conducting layer, lithium ions migrate from the LiCoO 2 layer to the first silicon layer by way of the LiPON layer.

18. The memory device of claim 17 , wherein the LiCoO 2 layer has a thickness of between 250 and 350 nanometers.

Assignees

• Nat Tech & Eng Solutions Sandia Llc

Inventors

• El Gabaly Marquez Farid
• Talin Albert Alec

Classifications

• H01L23/49866

  Electricity · mapped topic

• G11C5/14

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title

• H01L23/498

  Electricity · mapped topic

• G11C7/22 Primary

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• H01L27/112

  Electricity · mapped topic