Droop detection for low-dropout regulator

Patent metadata

Field	Value
Publication number	US-9946278-B2
Application number	US-201514720385-A
Country	US
Kind code	B2
Filing date	May 22, 2015
Priority date	May 22, 2015
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

A processor system includes first and second regulators for regulating an adjusted supply voltage. In one embodiment, the regulator system comprises a digital low-dropout (DLDO) control system comprising first and second regulators that generate a plurality of control signals to regulate an adjusted power supply voltage and that generate a charge when a droop level falls below a droop threshold value. The first regulator implements a first control loop and the second regulator implements a second and much faster acting control loop. A supply adjustment block with the two regulators and control loops are provided for each processor core allowing different cores to have different regulated supply levels all based on one common supply.

First claim

What is claimed is:

1. A processor system comprising:
a power supply voltage input for receiving a supply voltage from an external voltage supply;
at least one supply adjustment block comprising a plurality of selectable resistive elements for regulating an adjusted supply voltage based on said power supply voltage and a control signal; and
at least one processor core having:
a first input for receiving the supply voltage;
a digital low-dropout (DLDO) control system further comprising:
a first regulator coupled to receive a target supply voltage indication to produce the control signal to said supply adjustment block, wherein said first regulator and said at least one supply adjustment block are part of a first regulation loop having a first bandwidth;
a second regulator coupled to generate a charge injection signal based upon a detected droop when a droop level of the supply voltage falls below a droop threshold value, wherein said second regulator and said at least one supply adjustment block are part of a second regulation loop having a second bandwidth such that said second regulation loop operates faster than said first regulation loop; and
charge injection logic configured to inject a charge to said at least one processor core when the charge injection signal is asserted wherein said charge injection logic is coupled to said supply adjustment block; and

wherein said at least one supply adjustment block is connected between said at least one processor core and at least one of said power supply voltage input and circuit common or ground.

2. The processor system of claim 1 wherein each of said selectable resistive elements comprise a FET that further includes a gate terminal coupled to receive at least a portion of said control signal to selectively activate said FETs.

3. The processor system of claim 1 further including a plurality of processor core modules wherein each of said plurality of processor core modules has a corresponding DLDO control system connected to receive the supply voltage to generate said adjusted supply voltage and said charge injections to said processor core modules.

4. The processor system of claim 1 wherein said first regulator of said DLDO control system comprises a configurable digital proportional-integral-derivative (PID) controller and said second regulator comprises a fast droop detector (FDD) and wherein said FDD of said DLDO control system comprises a sigma-delta digital-to-analog converter (DAC) coupled to receive said droop threshold value to produce an analog droop threshold voltage.

5. The processor system of claim 4 wherein said FDD of said DLDO control system comprises an analog comparator coupled to receive said supply voltage and said analog droop threshold voltage from said DAC, wherein said comparator produces the charge injection signal whenever said supply voltage is equal to or less than said analog droop threshold voltage.

6. A method for providing supply voltages to a multi-core processor, comprising:
receiving a power supply voltage and a control signal and generating an adjusted supply voltage based upon the power supply voltage and the control signal;
receiving, at a first regulator, a target supply voltage indication and a supply voltage level indication and producing said control signal to a supply adjustment block based upon a difference in said target supply voltage indication and said supply voltage level indication with a first bandwidth;
comparing, in a second regulator, the adjusted supply voltage relative to a droop threshold level;
based on said comparing, generating a charge injection signal when said adjusted supply voltage falls below the droop threshold value with a second bandwidth such that said generating said charge injection signal operates faster than said producing said control signal; and
injecting a charge to at least one processor core of said multi-core processor based upon said charge injection signal.

7. The method of claim 6 further including, at said second regulator, receiving said droop threshold level in a digital form and converting to an analog droop threshold voltage and comparing said analog droop threshold voltage to the adjusted supply voltage.

8. The method of claim 7 wherein said first regulator comprises a digital low-dropout (DLDO) controller and said second regulator comprises a fast droop detector (FDD).

9. The method of claim 8 further including injecting a charge based upon a control word value produced by said DLDO controller when said supply voltage is less than said analog droop threshold voltage.

10. The method of claim 6 where said first regulator is a low bandwidth low power regulator, the method including selecting a first regulator set point to be a higher regulation set point relative to a second regulator set point of said second regulator.

11. The method of claim 6 wherein said second regulator is a fast response regulator, the method including selecting a second regulator set point to be a lower regulator set point relative to a first regulator set point of said first regulator.

12. The method of claim 6 further including receiving a first set point for said first regulator and a second set point for said second regulator from a power control block wherein said first set point is a target supply voltage level and said second set point is said droop threshold level and further wherein said first set point is greater than said second set point.

Assignees

• Advanced Micro Devices Inc

Inventors

• Rodriguez Miguel
• Kosonocky Stephen Victor
• Rachala Ravinder Reddy

Classifications

• H02M7/062

  Avoiding or suppressing excessive transient voltages or currents · CPC title

• H02M7/125

  Avoiding or suppressing excessive transient voltages or currents · CPC title

• G05F1/562

  with a threshold detection shunting the control path of the final control device · CPC title

• G05F1/56 Primary

  using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence) · CPC title

• G05F1/62

  using bucking or boosting DC sources · CPC title