Semiconductor structure and method

Patent metadata

Field	Value
Publication number	US-9945048-B2
Application number	US-201213525041-A
Country	US
Kind code	B2
Filing date	Jun 15, 2012
Priority date	Jun 15, 2012
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

A system and method for providing support to semiconductor wafer is provided. An embodiment comprises introducing a vacancy enhancing material during the formation of a semiconductor ingot prior to the semiconductor wafer being separated from the semiconductor ingot. The vacancy enhancing material forms vacancies at a high density within the semiconductor ingot, and the vacancies form bulk micro defects within the semiconductor wafer during high temperature processes such as annealing. These bulk micro defects help to provide support and strengthen the semiconductor wafer during subsequent processing and helps to reduce or eliminate a fingerprint overlay that may otherwise occur.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
providing a semiconductor raw material;
introducing a vacancy enhancing raw material into the semiconductor raw material, wherein the introducing the vacancy enhancing raw material is introduced at least in part through an ambient environment at a flow rate of between about 1 slm and about 100 slm, wherein the introducing the vacancy enhancing raw material introduces a concentration of vacancy enhancing raw material within the semiconductor raw material of between about 1E10 atom/cm 3 and about 1E19 atoms/cm 3 ;
crystallizing the semiconductor raw material and the vacancy enhancing material into a semiconductor ingot, wherein the semiconductor ingot comprises a first set of vacancies and has an interstitial oxygen concentration greater than 1.5×10 18 atoms/cm 3 and less than 1×10 19 atoms/cm 3 ;
separating a semiconductor wafer from the semiconductor ingot, the semiconductor wafer comprising the first set of vacancies;
forming a trench within the semiconductor wafer;
filling the trench with a dielectric;
annealing the dielectric within the trench and transforming the first set of vacancies into bulk micro defects using at least in part a thermal process, wherein the thermal process is performed between 1100° C. and 1150° C. for a time period of between 2 hours and 17 hours;
prior to the annealing the dielectric, increasing a temperature from ambient to between about 700° C. and about 1000° C. at a rate of between about 15° C./min and about 1000° C./min;
after the increasing the temperature holding the temperature within a range of between about 850° C. and about 980° C. for a time of between about 0.5 minutes and about 60 minutes; and
after the holding the temperature, increasing the temperature to greater than 1100° C. and less than 1300° C. at a rate of between about 0.5° C./min and about 5° C./min.

2. The method of claim 1 , further comprising planarizing the dielectric.

3. The method of claim 1 , wherein the vacancy enhancing raw material is a nitrogen gas.

4. A method of manufacturing a semiconductor device, the method comprising:
placing a semiconductor raw material into a crucible;
introducing nitrogen into the crucible, wherein the nitrogen is introduced as silicon oxynitride or silicon boron nitride;
mixing the semiconductor raw material and the nitrogen to form a semiconductor melt with a nitrogen concentration of greater than about 1×10 10 atoms/cm 3 and less than 1×10 13 atoms/cm 3 ;
pulling a semiconductor ingot from the semiconductor melt, the semiconductor ingot comprising the nitrogen and having an interstitial oxygen concentration greater than 1.5×10 18 atoms/cm 3 and less than 1×10 19 atoms/cm 3 ;
separating the semiconductor ingot into semiconductor wafers;
forming trenches within at least one of the semiconductor wafers;
forming a dielectric material within the trenches of the at least one of the semiconductor wafers;
annealing both the dielectric material and the at least one of the semiconductor wafers to generate bulk micro defects in the at least one of the semiconductor wafers, wherein the annealing process is performed for a time of greater than five minutes at a temperature of greater than 1100° C. and less than 1300° C.;
prior to the annealing both the dielectric material and the at least one of the semiconductor wafers, increasing a temperature from ambient to between about 700° C. and about 1000° C. at a rate of between about 15° C./min and about 1000° C./min;
after the increasing the temperature holding the temperature within a range of between about 85° C. and about 980° C. for a time of between about 0.5 minutes and about 60 minutes; and
after the holding the temperature, increasing the temperature to greater than 1100° C. and less than 1300° C. at a rate of between about 0.5° C./min and about 5° C./min.

5. The method of claim 4 , further comprising annealing the at least one of the semiconductor wafers and the dielectric material a second time.

6. The method of claim 5 , further comprising grinding the dielectric material prior to the annealing the at least one of the semiconductor wafers and the dielectric material the second time.

7. The method of claim 4 , wherein the semiconductor ingot has a vacancy concentration of greater than about 1×10 10 #/cm 3 and less than about 1×10 15 #/cm 3 .

Assignees

• Syue Sen Hong
• Chen Pu Fang
• Wang Shiang Bau
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Syue Sen-Hong
• Chen Pu-Fang
• Wang Shiang-Bau

Classifications

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P90/12

  Preparing bulk and homogeneous wafers · CPC title

• H10P50/28

  of insulating materials · CPC title

• H10P36/20

  Intrinsic gettering, i.e. thermally inducing defects by using oxygen present in the silicon body · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title