Semiconductor device having compensation capacitor to stabilize power supply voltage

Patent metadata

Field	Value
Publication number	US-9337139-B2
Application number	US-201313800978-A
Country	US
Kind code	B2
Filing date	Mar 13, 2013
Priority date	Mar 30, 2012
Publication date	May 10, 2016
Grant date	May 10, 2016

Abstract

Disclosed herein is a device that includes: first and second memory cell arrays arranged in a first direction; a plurality of first bump electrodes disposed between the first and second memory cell arrays and arranged in line in a second direction crossing the first direction; a plurality of second bump electrodes disposed between the first bump electrodes and the second memory cell arrays and arranged in line in the second direction; a first area being between the first and second bump electrodes; a plurality of third bump electrodes disposed in the first area; and a first capacitor formed in the third area.

First claim

What is claimed is:

1. A device comprising:
first and second memory cell arrays arranged in a first direction;
a plurality of first bump electrodes disposed between the first and second memory cell arrays and arranged in line in a second direction crossing the first direction;
a plurality of second bump electrodes disposed between the first bump electrodes and the second memory cell arrays and arranged in line in the second direction;
a first area being between the first and second bump electrodes; a plurality of third bump electrodes disposed in the first area;
a first capacitor formed in the first area;
a first power supply bump electrode being one of the first, second and third bump electrodes and supplied with a first power supply voltage;
a second power supply bump electrode being one of remaining ones of the first, second and third bump electrodes and supplied with a second power supply voltage different from the first power supply voltage;
a first interconnection line including a first portion that is vertically arranged with and coupled to the first power supply bump and a second portion that is disposed in the first area; and
a second interconnection line including a third portion that is vertically arranged with and coupled to the second power supply bump and a fourth portion that is disposed in the first area;
wherein the first capacitor includes first and second electrodes, the second portion of the first interconnection line serves as the first electrode of the capacitor and the fourth portion of the second interconnection line serves as the second electrode of the capacitor.

2. The device as claimed in claim 1 , wherein each of the first and second interconnection line is formed as a first wiring layer.

3. The device as claimed in claim 2 , further comprising:
a semiconductor substrate,
a multi-level wiring layer including the first wiring layer and a second wiring layer formed over the first wiring layer,
a third interconnection line formed as the second wiring layer and including a fifth portion that is vertically arranged with and coupled to the first power supply bump and a sixth portion that disposed in the first area and vertically arranged with the fourth portion of the second interconnection line, the sixth portion serving as the first electrode of the first capacitor, and
a fourth interconnection line formed as the second wiring layer and including a seventh portion that is vertically arranged with and coupled to the second power supply bump electrode and an eighth portion that is disposed in the first area and vertically arranged with the second portion of the first interconnection line, the eighth portion serving as the second electrode of the first capacitor.

4. The device as claimed in claim 3 , wherein the multi-level wiring layer further includes a third wiring layer formed over the first and second wiring layers, the device further comprises:
a fifth interconnection line formed as the third wiring layer and including a ninth portion that is vertically arranged with and coupled to the first power supply bump and a tenth portion that is disposed in the first area and vertically arranged with the second and portion of the first interconnection line and the eighth portion of the fourth interconnection line, the tenth portion serving as the first electrode of the first capacitor, and
a sixth interconnection line formed as the third wiring layer and including an eleventh portion that is vertically arranged with and coupled to the second power supply bump electrode and a twelfth portion that is disposed in the first area and vertically arranged with the fourth portion of the second interconnection line and sixth portion of the third interconnection line, the twelfth portion serving as the second electrode of the first capacitor.

5. The device as claimed in claim 1 , wherein each of the first and second memory cell arrays includes a plurality of storage capacitors and the first capacitor is substantially equal in structure to each of the storage capacitors.

6. The device as claimed in claim 1 , further comprising a semiconductor substrate, and wherein the first area includes a diffusion layer formed in the semiconductor substrate and a gate electrode formed on the diffusion layer with an intervention of an insulating film, the first capacitor includes first and second electrodes, the diffusion layer serves as the first electrode of the capacitor and the electrode serves as the second electrode of the capacitor.

7. The device as claimed in claim 6 , further comprising:
a first power supply bump electrode being one of the first, second and third bump electrodes and supplied with a first power supply voltage, the first power supply bump being electrically coupled to the diffusion layer, and
a second power supply bump electrode being one of remaining ones of the first, second and third bump electrodes and supplied with a second power supply voltage different from the first power supply voltage, the second power supply bump being electrically coupled to the gate electrode.

8. The device as claimed in claim 1 , further comprising:
a semiconductor substrate,
a plurality of first penetration electrodes penetrating the semiconductor substrate, each of the first penetration electrodes being coupled to a corresponding one of the first bump electrodes,
a plurality of second penetration electrodes penetrating the semiconductor substrate, each of the second penetration electrodes being coupled to a corresponding one of the second bump electrodes, and
a plurality of third penetration electrodes penetrating the semiconductor substrate and disposed in the first area, each of the third penetration electrodes being coupled to a corresponding one of the third bump electrodes.

9. A device comprising:
first and second memory cell arrays;
a first data input/output circuit that performs a data transfer from and to the first memory cell array;
a second data input/output circuit that performs a data transfer from and to the second memory cell array;
a plurality of first bump electrodes arranged in a first area which is positioned between the first data input/output circuit and the second data input/output circuit;
a power compensation capacitor provided in the first area; and
first and second electrode patterns each formed as a first wiring layer, wherein the first bump electrodes include a first one of the first bump electrodes connected to the first electrode pattern and supplied with a first power supply potential, and a second one of first bump electrodes connected to the second electrode pattern and supplied with a second power supply potential which is different from the first power supply potential, the first and second ones of the first bump electrodes coupled respectively to the first and second electrode patterns, and the power compensation capacitor includes a first capacitor electrode including a first portion that extends from the first electrode pattern as the first wiring layer, and a second capacitor electrode including a second portion that extends from the second electrode pattern as the first wiring layer.

10. The device as claimed in claim 9 , further comprising:
a substrate, and
a plurality of penetration electrodes each penetrating through the substrate, each of the penetration electrodes being connected to a corresponding one of the first bump electrodes.

11. The device as claimed in claim 9 , wherein the first bump electrodes further include a third one of the first bump electrodes that is connected to the first data input/output circuit, the third one of the first bump electrodes being connected to a signal electrode pattern that is formed as

Assignees

• Ps4 Luxco Sarl

Inventors

• Kitano Tomohiro
• Nagamine Hisayuki

Classifications

• H10W20/212

  Top-view shapes or dispositions, e.g. top-view layouts of the vias · CPC title

• H10W20/217

  comprising ring-shaped isolation structures outside of the via holes · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title