Analog to digital converter error rate reduction

Patent metadata

Field	Value
Publication number	US-9941896-B2
Application number	US-201615294227-A
Country	US
Kind code	B2
Filing date	Oct 14, 2016
Priority date	Oct 15, 2015
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

An analog-to-digital converter (ADC) may include a comparator and a metastability detector. The comparator may be configured to compare an input signal to a reference signal to determine whether the input signal exceeds the reference signal. The comparator may also be configured to output a comparator output based on the determination. An ADC output may be based at least in part on the comparator output. The metastability detector may be coupled to the comparator and may be configured to determine, based at least in part on the comparator output, that the comparator is operating under metastable conditions and may output a metastability detector output.

First claim

What is claimed is:

1. An analog-to-digital converter (ADC), comprising:
a first comparator configured to compare an input signal to a reference signal to determine whether the input signal exceeds the reference signal and output a comparator output based on the determination, wherein an ADC output is based at least in part on the comparator output; and
a metastability detector coupled to the first comparator and configured to determine, based at least in part on the comparator output, that the first comparator is operating under metastable conditions and output a metastability detector output, wherein metastability occurs when output of the first comparator represents neither a digital 1 nor a digital 0 determined when:
abs ( Op−Om )< Vx
where: Op is a positive output of a differential output of the first comparator;
Om is a negative output of a differential output of the first comparator;
Vx is a predetermined reference level;
Abs (x) corresponds to the absolute value of x; and

wherein the metastability detector comprises a second comparator, the second comparator coupled to an output of the first comparator.

2. The ADC of claim 1 , wherein the metastability detector is coupled to a digital backend configured to correct an error in the ADC output by replacing the ADC output with an estimated output.

3. The ADC of claim 2 , wherein the estimated output is determined by the digital backend based at least in part on the reference signal.

4. The ADC of claim 2 , wherein the digital backend retrieves the estimated output from a data store based at least in part on the metastability detector output.

5. The ADC of claim 1 , wherein the metastability detector comprises at least one of an exclusive OR (XOR) digital logic gate, a negative OR (NOR) digital logic gate, and an AND digital logic gate.

6. The ADC of claim 1 , wherein the metastability detector further comprises a logic gate, the logic gate coupled to an output of the second comparator.

7. The ADC of claim 1 , wherein the metastability detector further comprises a latch coupled to the output of the second comparator.

8. A pipelined apparatus, comprising:
a segment configured to receive an input signal, the segment comprising:
an analog-to-digital converter (ADC) comprising:
a first comparator configured to:
receive the input signal,
compare the input signal to a reference signal to determine whether the input signal exceeds the reference signal, and
output a comparator output based on the determination;
a metastability detector coupled to the first comparator and configured to determine that the first comparator is operating under metastable conditions and output a metastability detector output, wherein the determining that the first comparator is operating under metastable conditions comprises determining that metastability occurs when output of the first comparator represents neither a digital 1 nor a digital 0 determined when:
abs ( Op−Om )< Vx

where: Op is a positive output of a differential output of the first comparator;
 Om is a negative output of a differential output of the first comparator;
 Vx is a predetermined reference level;
 Abs (x) corresponds to the absolute value of x;

and wherein the metastability detector comprises a second comparator, the second comparator coupled to an output of the first comparator;
an encoder coupled to the ADC and configured to receive the comparator output and generate an ADC output based at least in part on the comparator output;
a digital-to-analog converter (DAC) coupled to the ADC and the encoder and configured to convert the ADC output to an analog output signal; and
a subtractor coupled to the input signal and the DAC and configured to subtract the analog output signal from the input signal to form a residual output signal.

9. The pipelined apparatus of claim 8 , wherein the segment further comprises an amplifier coupled to the subtractor and configured to amplify the residual output signal received from the subtractor.

10. The pipelined apparatus of claim 8 , further comprising a digital backend coupled to the metastability detector and configured to correct the ADC output when the metastability detector indicates that the first comparator is operating under metastable conditions.

11. The pipelined apparatus of claim 10 , wherein the digital backend corrects the ADC output by replacing the ADC output with an estimated output.

12. The pipelined apparatus of claim 11 , wherein the digital backend determines the estimated output based at least on a magnitude of the reference signal.

13. The pipelined apparatus of claim 8 , wherein the metastability detector comprises at least one of an exclusive OR (XOR) digital logic gate, a negative OR (NOR) digital logic gate, and an AND digital logic gate.

14. A method of analog-to-digital converter (ADC) metastability detection and correction, comprising:
receiving, by an ADC, an analog input signal for conversion to a digital value as an ADC output;
comparing, by a first comparator of the ADC, the analog input signal to a reference signal to generate a comparator output;
determining, by a second comparator of a metastability detector, that the first comparator is operating under metastable conditions wherein metastability occurs when output of the first comparator represents neither a digital 1 nor a digital 0 determined when:
abs ( Op−Om )< Vx

where: Op is a positive output of a differential output of the first comparator;
Om is a negative output of a differential output of the first comparator;
Vx is a predetermined reference level;
Abs (x) corresponds to the absolute value of x;

to generate a detector output based on the first comparator output; and
replacing, by a digital backend, the ADC output with an estimated output upon the digital backend receiving the detector output indicating that the first comparator is operating under metastable conditions.

15. The method of claim 14 , wherein replacing the ADC output with the estimated output comprises determining a nominal output of the first comparator, based at least in part on the reference signal, as the estimated output.

16. The method of claim 14 , wherein replacing the ADC output with the estimated output further comprises retrieving the estimated output from a data store based at least in part on the detector output.

17. The method of claim 15 , wherein the metastability detector comprises at least one of an exclusive OR (XOR) digital logic gate, a negative OR (NOR) digital logic gate, and an AND digital logic gate.

18. The method of claim 14 , further comprising:
transmitting the estimated output to a digital-to-analog converter (DAC) in a segment of the ADC, wherein the ADC is a pipelined ADC.

Assignees

• Texas Instruments Inc

Inventors

• El-Chammas Manar Ibrahim

Classifications

• H03M1/164

  the steps being performed sequentially in series-connected stages (H03M1/161 takes precedence) · CPC title

• H03M1/129 Primary

  Means for adapting the input signal to the range the converter can handle, e.g. limiting, pre-scaling (H03M1/18 takes precedence); Out-of-range indication · CPC title