Circuit and method for compensating noise

Patent metadata

Field	Value
Publication number	US-9941889-B1
Application number	US-201715590730-A
Country	US
Kind code	B1
Filing date	May 9, 2017
Priority date	Apr 18, 2017
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

A circuit for compensating quantized noise in fractional-N frequency synthesizer, comprising a PLL circuit that locks a phase compensated signal to a phase of a reference phase, wherein the phase lock loop circuit comprises a frequency divider and a phase frequency detector; a sigma-delta modulation and phase difference calculator coupled to the frequency divider generating an accumulated phase error by accumulating all previous differences between an input of the frequency divider and an output of the frequency divider within a period; a digital controlled delay line coupled to both the frequency divider and the SDM and Phase Difference calculator and generates the phase compensated signal by multiplying the accumulated phase error with a delay control word; and the phase frequency detector further generates a phase error by comparing the phase compensated signal with the reference clock.

First claim

What is claimed is:

1. A circuit for compensating quantized noise in fractional-N frequency synthesizer, comprising
a Phase Lock Loop (PLL) circuit, configured to lock a phase compensated signal to a phase of a reference phase, wherein the phase lock loop circuit comprises a frequency divider and a phase frequency detector;
a SDM (sigma-delta modulation) and phase difference calculator coupled to the frequency divider and configured to generate an accumulated phase error by accumulating all previous differences between an input of the frequency divider and an output of the frequency divider within a period;
a digital controlled delay line coupled to both the frequency divider and the SDM and Phase Difference calculator and configured to generate the phase compensated signal by multiplying the accumulated phase error with a delay control word, wherein the delay control word is derived from a module that takes a reference clock and a calibration clock as an input; and the phase frequency detector is further configured to generate a phase error by comparing the phase compensated signal with the reference clock.

2. The circuit of claim 1 , further comprising a delay calibration circuit coupled to both the digital controlled delay line and the SDM and phase difference calculator and is configured to calibrate the delay control word.

3. The circuit of claim 2 , wherein the delay calibration circuit further comprises a delay calibration logic circuit and a calibration controller, wherein the calibration controller is configured to determine whether a device works in calibration mode or in operation mode; and the delay calibration logic circuit is coupled to the calibration controller and is configured to generate the delay control word if the calibration controller determines that the device works in calibration mode.

4. The circuit of claim 1 , wherein the SDM and phase difference calculator further comprises a sigma-delta modulator and an instantaneous phase difference calculator;
wherein the instantaneous phase difference calculator is configured to generate an instantaneous phase difference by subtracting an instantaneous input of the frequency divider from an instantaneous output of the frequency divider; and
the sigma-delta modulator is coupled to the instantaneous phase difference calculator and is configured to generate the accumulated phase error by accumulating all previous instantaneous phase differences between the input of the frequency divider and the output of the frequency divider within the period.

5. The circuit of claim 1 , wherein the digital controlled delay line further comprises a variable delay line and a fixed delay line,
wherein the fixed delay line is configured to be enabled in a calibration mode and be disabled in an operation mode, and
the fixed delay line and the variable delay line form a closed loop in the calibration mode.

6. The circuit of claim 5 , wherein the variable delay line has a fixed bitwidth.

7. The circuit of claim 1 , wherein
the phase frequency detector is configured to receive the phase compensated signal and the reference clock, and to output controls signals according to phase and frequency difference between the phase compensated signal and the reference clock; wherein
the PLL circuit further comprises—
a charge pump coupled to the phase frequency detector, configured to generate a current according to the control signals;
a filter coupled to the charge pump, configured to generate a voltage according to the current;
a voltage controlled oscillator (VCO) coupled to the filter, configured to generate an oscillation frequency according to the voltage; and
wherein the frequency divider coupled to the VCO and configured to receive the oscillation frequency, to divide the oscillation frequency, and to generate the output of the frequency divider.

8. A method of compensating quantized noise in fractional-N frequency synthesizer, comprising
locking, by a phase lock loop, a noise compensated signal to a reference phase, wherein the phase lock loop circuit comprises a frequency divider and a phase frequency detector;
generating, by a SDM (sigma-delta modulation) and phase difference calculator, an accumulated phase error by accumulating all previous differences between an input of the frequency divider and an output of the frequency divider within a period;
generating, by a digital controlled delay line, a phase compensated signal by multiplying the accumulated phase error with a delay control word, wherein the delay control word is derived from a module that takes a reference clock and a calibration clock as an input;
calibrating, by a delay calibration circuit, the delay control word; and
generating, by the phase frequency detector, a phase error by comparing a compensated phase with the reference clock.

9. The method of claim 8 , further comprising
determining, by a calibration controller, whether a device works in calibration mode or in operation mode; and
generating, by a delay calibration logic circuit, the delay control word if the calibration controller determines that the device works in calibration mode.

10. The method of claim 8 , further comprising:
generating, by an instantaneous phase difference calculator, an instantaneous phase difference by subtracting an instantaneous input of the frequency divider from an instantaneous output of the frequency divider; and
generating, by a sigma-delta modulator, the accumulated phase error by accumulating all previous instantaneous phase differences between an input of the frequency divider and an output of the frequency divider within the period.

11. The method of claim 8 , wherein the digital controlled delay line further comprises a variable delay line and a fixed delay line, the method further comprises
enabling the fixed delay line in a calibration mode and disabling the fixed delay line in an operation mode, and
forming, by the fixed delay line and the variable delay line, a closed loop in the calibration mode.

12. The method of claim 11 , wherein the variable delay line has a fixed bitwidth.

13. The method of claim 8 , further comprising
receiving, by the phase frequency detector, the compensated phase and the reference clock, and to output control signals according to phase and frequency difference between the compensated phase and the reference clock;
generating, by a charge pump, a current according to the control signals;
generating, by a filter, a voltage according to the current;
generating, by a voltage controlled oscillator (VCO), an oscillation frequency according to the voltage; and
receiving the oscillation frequency, dividing the oscillation frequency, and generating the output by the frequency divider.

Assignees

• Beken Corp

Inventors

• Guo Dawei
• Yu Caogang

Classifications

• H03L7/0805 Primary

  the loop being adapted to provide an additional control signal for use outside the loop · CPC title

• H03K5/133

  using a chain of active delay devices · CPC title

• H03L7/1976

  using a phase accumulator for controlling the counter or frequency divider · CPC title

• H03D3/241

  the oscillator being part of a phase locked loop · CPC title

• G06F7/49942

  Significance control · CPC title