Semiconductor device and method for manufacturing a semiconductor device

Patent metadata

Field	Value
Publication number	US-9941403-B2
Application number	US-201213627215-A
Country	US
Kind code	B2
Filing date	Sep 26, 2012
Priority date	Sep 26, 2012
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

A semiconductor device includes a transistor including a source region, a drain region, and a gate electrode. The gate electrode is disposed in a first trench arranged in a top surface of the semiconductor substrate. The device further includes a control electrode. The control electrode is disposed in a second trench arranged in the top surface of the semiconductor substrate. The second trench has a second shape that is different from a first shape of the first trench.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first transistor at least partially formed in a semiconductor substrate, the first transistor comprising a first drift zone; and
a plurality of second transistors connected in series to form a series circuit, the series circuit being connected in series with the first transistor to form a further series circuit, the further series circuit implementing an active drift zone field effect transistor, at least one of the second transistors comprising:
a plurality of trenches in a top surface of the semiconductor substrate; and
a plurality of transistor cells, each of the transistor cells comprising a second gate electrode, the second gate electrodes being disposed in the trenches;
wherein the second gate electrodes of different transistor cells are electrically coupled to each other, second source regions of different transistor cells are electrically coupled to each other, and second drain regions of different transistor cells are electrically coupled to each other;
wherein a lateral distance between the trenches is such that, depending on a doping impurity concentration of a body region, the body region between adjacent inversion layers formed at a boundary between the body region and a gate dielectric material at the second gate electrodes is completely depleted responsive to a voltage corresponding to at least a threshold voltage of the second transistor being applied to the second gate electrode; and
wherein the semiconductor substrate comprises a buried doped layer, the second source regions or the second drain regions of the second transistor cells being disposed in the buried doped layer.

2. The semiconductor device according to claim 1 , wherein a lateral distance between adjacent trenches is less than 120 nm.

3. The semiconductor device according to claim 1 , wherein the first transistor and the plurality of second transistors are disposed adjacent to the top surface of the semiconductor substrate.

4. The semiconductor device according to claim 1 , wherein adjacent ones of the second transistors are connected by means of second contact trenches formed in the top surface of the semiconductor substrate and transistor interconnects.

5. The semiconductor device according to claim 4 , wherein the transistor interconnects are disposed over the top surface of the semiconductor substrate.

6. The semiconductor device according to claim 1 , wherein the first transistor further comprises a first drain region, the first drain region and the second drain regions being arranged in the buried layer.

7. A semiconductor device comprising:
a first transistor comprising a first drift zone; and
a plurality of second transistors connected in series to form a series circuit, the series circuit being connected in series with the first transistor to form a further series circuit, the further series circuit implementing an active drift zone field effect transistor,
the first transistor and the plurality of second transistor being formed in a semiconductor substrate comprising a buried layer,
each of the second transistors comprising:
transistor cells connected in parallel, each of the transistor cells comprising a second gate electrode, the second gate electrodes being disposed in gate trenches arranged in a top surface of the semiconductor substrate, second source regions or second drain regions of the transistor cells being arranged in the buried layer, wherein a lateral distance d between the gate trenches fulfills the following formula:
d< 2 ×Wm,

wherein Wm denotes a maximum width of a surface depletion region formed in the semiconductor substrate.

8. The semiconductor device according to claim 7 , wherein a lateral distance between adjacent trenches is less than 120 nm.

9. The semiconductor device according to claim 7 , wherein the first transistor and the plurality of second transistors are disposed adjacent to the top surface of the semiconductor substrate.

10. The semiconductor device according to claim 7 , wherein adjacent ones of the second transistors are connected by means of second contact trenches formed in the top surface of the semiconductor substrate and transistor interconnects.

11. The semiconductor device according to claim 10 , wherein the transistor interconnects are disposed over the top surface of the semiconductor substrate.

Assignees

• Infineon Technologies Ag

Inventors

• Schloesser Till
• Zundel Markus

Classifications

• H01L29/4236

  Electricity · mapped topic

• H01L29/0696

  Electricity · mapped topic

• H01L29/7813 Primary

  Electricity · mapped topic

• H01L21/823481

  Electricity · mapped topic

• H01L27/0883

  Electricity · mapped topic