Floating body contact circuit method for improving ESD performance and switching speed

Patent metadata

Field	Value
Publication number	US-9941347-B2
Application number	US-201715495819-A
Country	US
Kind code	B2
Filing date	Apr 24, 2017
Priority date	Nov 20, 2013
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

Embodiments of systems, methods, and apparatus for improving ESD performance and switching time for semiconductor devices including metal-oxide-semiconductor (MOS) field effect transistors (FETs), and particularly to MOSFETs fabricated on Semiconductor-On-Insulator (“SOI”) and Silicon-On-Sapphire (“SOS”) substrates.

First claim

What is claimed is:

1. An electronic circuit including:
(a) at least one field effect transistor (FET), each FET including:
(1) a gate, a drain, a source, and a body;
(2) a gate resistor series connected to the gate of such FET;
(3) an accumulated charge sink (ACS) circuit connected to the body of such FET; and
(4) an ACS resistance series connected to the ACS circuit, wherein the series-connected ACS resistance and the ACS circuit are connected to the gate resistor of such FET at a node opposite to the connection of the gate resistor to the gate; and

(b) at least one electrostatic discharge (ESD) protection electronic circuit, each ESD protection electronic circuit including:
(1) a selectable resistor coupled in series between a common control terminal for at least one FET and the gate resistor of at least one FET; and
(2) a bypass module coupled in parallel with the selectable resistor and having a control signal input for receiving a control signal, the bypass module being configured to respond to the control signal to (A) in a bypass mode, conduct signals applied to the coupled common control terminal through the bypass module and around the selectable resistor, and (B) in a protection mode, cause signals applied to the coupled common control terminal to be conducted through the selectable resistor, wherein in the bypass mode, the bypass module presents no significant added resistance, relative to the gate resistor of the at least one coupled FET, to signals applied to the coupled common control terminal.

2. The invention of claim 1 , wherein the resistance of the ACS resistance is sized to provide substantial ESD tolerance without substantially impairing the function of the ACS circuit.

3. The invention of claim 1 , wherein the resistance of the ACS resistance has at least 10 times the resistance of the gate resistor.

4. The invention of claim 1 , wherein the ACS circuit is a diode.

5. The invention of claim 1 , wherein the electronic circuit is fabricated as an integrated circuit on one of a semiconductor-on-insulator substrate or a silicon-on-sapphire substrate.

6. The invention of claim 1 , wherein at least one FET conducts radio frequency signals between its source and drain in response to a signal applied to the common control terminal.

7. The invention of claim 1 , wherein the bypass module includes a bypass FET having a gate, a drain, a source, and a gate resistor series connected to the gate of the bypass FET, wherein the source and drain of the bypass FET are coupled across the selectable resistor, and the gate resistor of the bypass FET is coupled to the control signal input.

8. The invention of claim 7 , wherein the bypass FET and the at least one FET are MOSFETs.

9. The invention of claim 8 , wherein the MOSFETs are floating body MOSFETs.

10. The invention of claim 1 , wherein the selectable resistor has twice or more resistance than the gate resistors.

11. The invention of claim 1 , wherein the protection mode persists when no electrical power is applied to the electronic circuit.

12. An integrated circuit including:
(a) at least two stacked field effect transistors (FET), each FET including:
(1) a gate, a drain, a source, and a body:
(2) a gate resistor series connected to the gate of such FET;
(3) an accumulated charge sink (ACS) circuit connected to the body of such FET; and
(4) an ACS resistance series connected to the ACS circuit, wherein the series-connected ACS resistance and the ACS circuit are connected to the gate resistor of such FET at a node opposite to the connection of the gate resistor to the gate; and

(b) at least one electrostatic discharge (ESD) protection electronic circuit, each ESD protection electronic circuit including:
(1) a selectable resistor coupled in series between a common control terminal for at least one FET and the gate resistor of at least one FET; and
(2) a bypass module coupled in parallel with the selectable resistor and having a control signal input for receiving a control signal, the bypass module being configured to respond to the control signal to (A) in a bypass mode, conduct signals applied to the coupled common control terminal through the bypass module and around the selectable resistor, and (B) in a protection mode, cause signals applied to the coupled common control terminal to be conducted through the selectable resistor, wherein in the bypass mode, the bypass module presents no significant added resistance, relative to the gate resistor of the at least one coupled FET, to signals applied to the coupled common control terminal.

13. The invention of claim 12 , wherein the resistance of the ACS resistance is sized to provide substantial ESD tolerance without substantially impairing the function of the ACS circuit.

14. The invention of claim 12 , wherein the resistance of the ACS resistance has at least 10 times the resistance of the gate resistor.

15. The invention of claim 12 , wherein the ACS circuit is a diode.

16. The invention of claim 12 , wherein the integrated circuit is fabricated on one of a semiconductor-on-insulator substrate or a silicon-on-sapphire substrate.

17. The invention of claim 12 , wherein at least one FET conducts radio frequency signals between its source and drain in response to a signal applied to the common control terminal.

18. The invention of claim 12 , wherein the bypass module includes a bypass FET having a gate, a drain, a source, and a gate resistor series connected to the gate of the bypass FET, wherein the source and drain of the bypass FET are coupled across the selectable resistor, and the gate resistor of the bypass FET is coupled to the control signal input.

19. The invention of claim 18 , wherein the bypass FET and the at least one FET are MOSFETs.

20. The invention of claim 19 , wherein the MOSFETs are floating body MOSFETs.

21. The invention of claim 12 , wherein the selectable resistor has twice or more resistance than the gate resistors.

22. The invention of claim 12 , wherein the protection mode persists when no electrical power is applied to the integrated circuit.

23. A method for improving electrostatic discharge tolerance and switching speed in an integrated circuit, including:
(a) providing at least one field effect transistor (FET), each FET including:
(1) a gate, a drain, a source, and a body;
(2) a gate resistor series connected to the gate of such FET;
(3) an accumulated charge sink (ACS) circuit connected to the body of such FET; and
(4) an ACS resistance series connected to the ACS circuit, wherein the series-connected ACS resistance and the ACS circuit are connected to the gate resistor of such FET at a node opposite to the connection of the gate resistor to the gate; and

(b) providing at least one electrostatic discharge (ESD) protection electronic circuit, each ESD protection electronic circuit including:
(1) a selectable resistor coupled in series between a common control terminal for at least one FET and the gate resistor of at least one FET; and
(2) a bypass module coupled in parallel with the selectable resistor and having a control signal input for receiving a control signal, the bypass module being configured to respond to the control signal to (A) in a bypass mode, conduct signals applied to the coupled common control terminal through the bypass module and around the selectable resistor, and (B) in a protection mode, cause signals applied to the coupled common control terminal to be conducted through

Assignees

• Peregrine Semiconductor Corp
• Psemi Corp

Inventors

• Shapiro Eric S
• Allison Matt

Classifications

• H01L29/78

  Electricity · mapped topic

• H03K17/04123

  in field-effect transistor switches · CPC title

• H01L28/20 Primary

  Electricity · mapped topic

• H01L27/1203

  Electricity · mapped topic

• H01L27/0629

  Electricity · mapped topic