Method of manufacturing thin film transistor substrate

Patent metadata

Field	Value
Publication number	US-9941313-B2
Application number	US-201614987615-A
Country	US
Kind code	B2
Filing date	Jan 4, 2016
Priority date	Jun 22, 2015
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

A method of manufacturing a thin film transistor substrate includes forming a semiconductor pattern on a substrate, wherein the semiconductor pattern includes a first area, a second area, and a third area, wherein the second area and the third area are located on each side of the first area; forming an insulating layer on the substrate to cover the semiconductor pattern; forming a metal pattern layer on the insulating layer using a first photosensitive pattern; doping the semiconductor pattern with first impurities using the first photosensitive pattern; forming a gate electrode by patterning the metal pattern layer using a second photosensitive pattern; and doping the semiconductor pattern with second impurities having a lower concentration than the first impurities.

First claim

What is claimed is:

1. A method of manufacturing a thin film transistor substrate, the method comprising:
forming a semiconductor pattern on a substrate, wherein the semiconductor pattern comprises a first area, a second area, and a third area, wherein the second area and the third area are located on each side of the first area;
forming an insulating layer on the substrate to cover the semiconductor pattern;
forming a metal pattern layer on the insulating layer using a first photosensitive pattern;
doping the semiconductor pattern with first impurities using the first photosensitive pattern;
forming a gate electrode by patterning the metal pattern layer using a second photosensitive pattern; and
doping the semiconductor pattern with second impurities having a lower concentration than the first impurities,
wherein the first area of the semiconductor pattern comprises a fourth area, a fifth area and a sixth area, the fourth area corresponds to a central portion of the first area, and the fifth area and the sixth area are located on each side of the fourth area,
wherein, a thickness of a portion of the first photosensitive pattern that corresponds to the fourth area is leas than a thickness of a portion corresponding to the fifth area and the sixth area.

2. The method of claim 1 , wherein the metal pattern layer is formed on a position corresponding to the first area of the semiconductor pattern.

3. The method of claim 1 , wherein doping the semiconductor pattern with first impurities comprises doping the second area and the third area of the semiconductor pattern with the first impurities.

4. The method of claim 1 , wherein the first photosensitive pattern is formed by using one of a slit mask and a half-tone mask.

5. The method of claim 1 , wherein the second photosensitive pattern is formed by a same mask process as that of the first photosensitive pattern.

6. The method of claim 1 , wherein the second photosensitive pattern is formed by ashing the first photosensitive pattern.

7. The method of claim 1 , wherein, a thickness of a portion of the second photosensitive pattern corresponding to the fifth area and the sixth area is less than the thickness of the portion of the first photosensitive pattern corresponding to the fifth area and the sixth area, and the second photosensitive pattern comprises an opening corresponding to the fourth area.

8. The method of claim 1 , wherein forming the gate electrode comprises forming a first gate electrode and a second gate electrode spaced apart from each other corresponding to the fifth area and the sixth area, respectively.

9. The method of claim 8 , wherein the fourth area of the semiconductor pattern corresponds to a space between the first gate electrode and the second gate electrode and is doped with only the second impurities.

10. The method of claim 8 , wherein a width of the first gate electrode and a width of the second gate electrode are less than a width of the fifth area and a width of the sixth area, respectively.

11. The method of claim 10 , wherein doping the semiconductor pattern with second impurities is performed using the gate electrode as a mask.

12. The method of claim 11 , Wherein the fourth area, a portion of the fifth area and a portion of the sixth area of the semiconductor pattern are doped with the second impurities.

13. A method of manufacturing a thin film transistor substrate, the method comprising:
forming a semiconductor pattern on a substrate;
forming a metal pattern layer on the semiconductor pattern using a first photosensitive pattern;
doping the semiconductor pattern with first impurities using the first photosensitive pattern;
forming a second photosensitive pattern using the first photosensitive pattern;
forming a gate electrode by patterning the metal pattern layer using the second photosensitive pattern to form a first gate electrode and a second gate electrode spaced apart from each other; and
doping the semiconductor pattern with second impurities having a lower concentration than the first impurities using the gate electrode as a mask.

14. The method of claim 13 , wherein the semiconductor pattern comprises a first area, a second area, and a third area, wherein the second area and the third area are disposed on each side of the first area, the metal pattern layer is formed on a position corresponding to the first area of the semiconductor pattern, and the first impurities are doped into the second area and the third area of the semiconductor pattern.

15. The method of claim 14 , wherein the first area of the semiconductor pattern comprises a fourth area, a fifth area and a sixth area, the fourth area corresponds to a central portion of the first area, and the fifth area and the sixth area are located on each side of the fourth area, wherein the first gate electrode and second gate electrode are formed corresponding to the fifth area and the sixth area, respectively, and the fourth area of the semiconductor pattern corresponds to a space between the first gate electrode and the second gate electrode.

16. The method of claim 15 , wherein a width of the first gate electrode and a width of the second gate electrode are less than a width of the fifth area and a width of the sixth area, respectively, and the fourth area, a portion of the fifth area and a portion of the sixth area of the semiconductor pattern are doped with the second impurities.

17. The method of claim 15 , wherein:
a thickness of a portion of the first photosensitive pattern that corresponds to the fourth area is less than a thickness of a portion corresponding to the fifth area and the sixth area; and
a thickness of a portion of the second photosensitive pattern corresponding to the fifth area and the sixth area is less than the thickness of the portion of the first photosensitive pattern corresponding to the fifth area and the sixth area, and the second photosensitive pattern comprises an opening corresponding to the fourth area.

18. The method of claim 14 , further comprising forming an insulating layer on the substrate to cover the semiconductor pattern,
wherein forming a metal pattern layer on the insulating layer using a first photosensitive pattern comprises sequentially stacking a metal layer and a photosensitive layer on the insulating layer, forming the first photosensitive pattern from the photosensitive layer using a photo mask, and etching the metal layer using the first photosensitive pattern as a mask to form the metal pattern layer.

Assignees

• Samsung Display Co Ltd

Inventors

• Ahn Kiwan
• Kim Junghyun
• Cho Seunghwan

Classifications

• H01L29/78645

  Electricity · mapped topic

• H01L29/78621

  Electricity · mapped topic

• H01L27/1288 Primary

  Electricity · mapped topic

• H01L29/66757

  Electricity · mapped topic

• H10D30/6733

  Multi-gate TFTs · CPC title