Stacked semiconductor die assemblies with improved thermal performance and associated systems and methods

Patent metadata

Field	Value
Publication number	US-9269700-B2
Application number	US-201414231101-A
Country	US
Kind code	B2
Filing date	Mar 31, 2014
Priority date	Mar 31, 2014
Publication date	Feb 23, 2016
Grant date	Feb 23, 2016

Abstract

Stacked semiconductor die assemblies with improved thermal performance and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a stack of semiconductor dies and a thermally conductive casing at least partially enclosing the stack of semiconductor dies within an enclosure. A package substrate carries the thermally conductive casing, and an interposer is disposed between the thermally conductive casing and the stack of semiconductor dies. A peripheral portion of the interposer extends laterally beyond the stack of semiconductor dies and is coupled to a plurality of conductive members interposed between the peripheral portion and the package substrate.

First claim

We claim:

1. A semiconductor die assembly, comprising:
a stack of semiconductor dies having a vertical height;
a thermally conductive casing;
an interposer between the thermally conductive casing and the stack of semiconductor dies, wherein a peripheral portion of the interposer extends laterally beyond the stack of semiconductor dies; a package substrate carrying the thermally conductive casing; and a plurality of conductive members interposed between the package substrate and the peripheral portion of the interposer, wherein each of the conductive members includes a solder bump having a vertical height that is about equal to or greater than the vertical height of the stack of semiconductor dies.

2. The die assembly of claim 1 wherein the thermally conductive casing includes:
a cap portion attached to a back side surface of the interposer; and
a wall portion extending vertically between the cap portion and the package substrate;
wherein the wall portion is attached to an outer surface of the package substrate.

3. The dies assembly of claim 2 wherein the stack of semiconductor dies includes:
a stack of memory dies; and
a logic die disposed between the stack of memory dies and the interposer.

4. The die assembly of claim 1 wherein the die assembly further comprises an interface material interposed between the package substrate and the stack of semi conductor dies.

5. The die assembly of claim 4 wherein:
the interface material is electrically insulative;
the stack of semiconductor dies includes an outermost die having a plurality of through substrate interconnects extending therethough; and
the plurality of through-substrate interconnects contact the irate ace material.

6. The dies assembly of claim 1 wherein the stack of semiconductor dies further comprises:
a stack of memory dies having a first footprint; and
a logic die having a second footprint that is larger than the first footprint along at least one axis of the stack of memory dies.

7. The dies assembly of claim 6 wherein the interposer has a third footprint that is larger than the second footprint along at least one axis of the logic die.

8. The dies assembly of claim 6 wherein the solder bump includes a metal solder ball.

9. The die assembly of claim 1 wherein the interposer includes a redistribution network electrically coupling the conductive members to the stack of semiconductor dies, and wherein the redistribution network includes a circuit element coupled between at least one of the conductive members and the stack of semiconductor dies.

10. The die assembly of claim 9 wherein the circuit element includes a capacitor.

11. A semiconductor die assembly, comprising: a thermally conductive casing; a package substrate, wherein the package substrate and the thermally conductive casing together define an enclosure, and wherein the package substrate includes a plurality of first bond pads;
an interposer attached to the thermally conductive casing within the enclosure, wherein the interposer includes a plurality of second bond pads facing corresponding ones of the first bond pads and separated therefrom by a gap;
a stack of semiconductor dies disposed between the interposer and the package substrate
within the enclosure, wherein the stack of semiconductor dies includes a first outermost die having an outer surface adjacent the interposer, and a second outermost die having an outer surface adjacent the package substrate, and wherein the outer surfaces of the first and second outermost dies are spaces apart from one another by a first distance; and
a plurality of solder bumps, wherein each of the solder bumps is attached to one of the first bond pads and a corresponding one of the second bond pads, and wherein each of the solder bumps extends a second distance across the gap that is about equal to or greater than the first distance.

12. The die assembly of claim 11 wherein the individual solder bumps include a metal solder ball.

13. A method of forming a semiconductor die assembly, comprising: attaching stack of semiconductor dies to an interposer, wherein the stack of semiconductor dies has a vertical height;
forming solder bumps between a package substrate and an active surface at a peripheral portion of the interposer;
attaching a thermally conductive casing to a back side surface of the interposer opposite the active surface to least partially enclose the interposer and the stack of semiconductor dies within an enclosure; and
attaching the stack of semiconductor dies to the package substrate such that the solder bumps extend vertically between the active surface and the package substrate, wherein the solder bumps have a vertical height that is about equal to or greater than the vertical height of the stack of semiconductor dies.

14. The method of claim 13 wherein the method further includes attaching the thermally conductive casing to the package substrate.

15. The method of claim 13 wherein forming the solder bumps includes attaching each of the solder bumps to a bond pad on the interposer and to a corresponding bond pad on the package substrate.

16. The method of claim 13 wherein forming the solder bumps includes attaching the solder bumps to first bond pads on the interposer and corresponding second bond pads on the package substrate.

17. The method of claim 13 wherein the stack of semiconductor dies includes a stack of memory dies attached to a logic die, and wherein attaching the stack of semiconductor dies to the interposer further includes attaching the logic die to the interposer between the interposer and the stack of memory dies.

18. The method of claim 17 , further comprising forming a redistribution network on the interposer that electrically couples the solder bumps to the stack of semi conductor dies.

19. The method of claim 18 wherein forming the redistribution network includes forming a circuit element electrically coupled between the stack of memory dies and the interposer.

20. The method of claim 19 wherein the circuit element includes a capacitor.

21. A semiconductor system, comprising:
a hybrid memory cube (HMC), including
a package substrate,
a thermally conductive casing defining an enclosure,
an interposer attached to the thermally conductive casing within the enclosure,
a stack of semiconductor dies on the interposer and within the enclosure, wherein the stack of dies projects from the interposer to a first height, and wherein the stack of dies includes a stack of memory dies and at least one logic die attached to the stack of memory dies, and
a plurality of solder bumps coupled between the interposer and the package substrate, wherein the plurality of solder bumps is adjacent to the stack of semiconductor dies, and wherein each of the solder bumps projects from the interposer to a second height that is about equal to or greater than the first height; and

a driver electrically coupled to the HMC via the package substrate.

Assignees

• Micron Technology Inc

Inventors

• Koopmans Michel
• Luo Shijian
• Hembree David R

Classifications

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W70/682

  comprising holes having chips therein · CPC title

• H10W90/297 Primary

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title