Integrated circuit packages including high density bump-less build up layers and a lesser density core or coreless substrate

Patent metadata

Field	Value
Publication number	US-9941245-B2
Application number	US-86092207-A
Country	US
Kind code	B2
Filing date	Sep 25, 2007
Priority date	Sep 25, 2007
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

In some embodiments, integrated circuit packages including high density bump-less build up layers and a lesser density core or coreless substrate are presented. In this regard, an apparatus is introduced having a first element including a microelectronic die having an active surface and at least one side, an encapsulation material adjacent said at least one microelectronic die side, wherein said encapsulation material includes at least one surface substantially planar to said microelectronic die active surface, a first dielectric material layer disposed on at least a portion of said microelectronic die active surface and said encapsulation material surface, a plurality of build-up layers disposed on said first dielectric material layer, and a plurality of conductive traces disposed on said first dielectric material layer and said build-up layers and in electrical contact with said microelectronic die active surface; and a second element coupled to the first element, the second element including a substrate having a plurality of dielectric material layers and conductive traces to conductively couple conductive contacts on a top surface with conductive contacts on a bottom surface, said conductive contacts on said top surface conductively coupled with said conductive traces of said first element. Other embodiments are also disclosed and claimed.

First claim

What is claimed is:

1. An apparatus comprising:
a plurality of first elements each including:
a microelectronic die having an active surface and at least one side,
an encapsulation material adjacent said at least one microelectronic die side, wherein said encapsulation material includes at least one surface substantially planar to said microelectronic die active surface,
a substrate forming a direct ace with the active surface and the encapsulation material, the substrate including:
a first dielectric material layer forming a substantially continuous, direct interface with at least a portion of said microelectronic die active surface and said encapsulation material surface,
a plurality of build-up layers disposed on said first dielectric material layer,
a plurality of conductive traces disposed on said first dielectric material layer and said build-up layers and in electrical contact with said microelectronic die active surface;
a second element coupled to said plurality of first elements, the second element including a substrate having a core, and a plurality of dielectric material layers and conductive traces built up on either side of the core, to conductively couple conductive contacts on a top surface with conductive contacts on a bottom surface, said conductive contacts on said top surface conductively coupled with said conductive traces of said plurality of first elements;

at least one memory device embedded within the plurality of dielectric material layers built up on at least one side of the core of the second component; and
a printed circuit board coupled to the conductive contacts on the bottom surface of the second element, the second element having the plurality of first elements coupled to the top surface of the second element.

2. The apparatus of claim 1 , wherein said plurality of first elements comprises four first elements.

3. The apparatus of claim 1 , wherein said plurality of first elements comprises sixteen first elements.

4. The apparatus of claim 1 , wherein said conductive contacts on said top surface of said second element comprise a pitch of from about 80 to about 130 micrometers.

5. The apparatus of claim 1 , wherein said conductive contacts on said bottom surface of said second element comprise a pitch of from about 400 to about 800 micrometers.

6. The apparatus of claim 1 , further comprising said plurality of first elements including a microelectronic package core having an opening in which said microelectronic die is disposed.

7. The apparatus of claim 1 , wherein said conductive contacts on said bottom surface of said second element comprise a land grid array.

8. The apparatus of claim 1 , wherein said conductive contacts on said bottom surface of said second element comprise a ball grid array.

9. The apparatus of claim 1 , wherein said conductive contacts on said top surface of said second element comprise bumps.

10. The apparatus of claim 1 , further comprising epoxy underfill between said plurality of first elements and said second element.

Assignees

• Skeete Oswald
• Mahajan Ravi
• Guzek John
• Intel Corp

Inventors

• Skeete Oswald
• Mahajan Ravi
• Guzek John

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W74/012

  of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills · CPC title