Control of warpage using ABF GC cavity for embedded die package

Patent metadata

Field	Value
Publication number	US-9941219-B2
Application number	US-201414491892-A
Country	US
Kind code	B2
Filing date	Sep 19, 2014
Priority date	Sep 19, 2014
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

Embodiments include semiconductor device packages and methods of forming such packages. In an embodiment, the package may include a die-side reinforcement layer with a cavity formed through the die-side reinforcement layer. A die having a first side and an opposite second side comprising a device side may be positioned in the cavity with the first side of the die being substantially coplanar with a first side of the die-side reinforcement layer. In an embodiment, a build-up structure may be coupled to a second side of the die. Embodiments include a build-up structure that includes a plurality of alternating layers of patterned conductive material and insulating material.

First claim

What is claimed is:

1. A device package comprising:
a die-side reinforcement layer having a first side and an opposite second side, wherein a cavity is formed through the die-side reinforcement layer, and wherein the die-side reinforcement layer is a glass cloth material and conductive traces are not formed into the die-side reinforcement layer;
a die having a first side and an opposite second side comprising a device side with contact points, wherein the die is positioned in the cavity with the first side of the die being substantially coplanar with the first side of the die-side reinforcement layer; and
a build-up structure coupled to and in direct contact with a second side of the die, the build-up structure comprising a plurality of alternating layers of patterned conductive material and insulating material, wherein at least one of the layers of patterned conductive material is coupled to one of the contact points of the die, wherein the device package further comprises a second die having a first side and an opposite second side comprising a device side with contact points, wherein the second die is positioned in the cavity with the first side of the second die being substantially coplanar with the first side of the die-side reinforcement layer.

2. The device package of claim 1 , wherein a gap separates sidewalls of the die from sidewalls of the cavity formed through the die-side reinforcement layer.

3. The device package of claim 2 , wherein a width of the gap is chosen to provide desired stiffness for the device package.

4. The device package of claim 3 , wherein the width of the gap is between 1.0 μm and 1.0 mm.

5. The device package of claim 2 , wherein the gap separating the sidewalls of the die from the sidewalls of the cavity is filled with an insulative material.

6. The device package of claim 5 , wherein the insulative material filling the gap separating the sidewalls of the die from the sidewalls of the cavity is the same insulating material used in the build-up structure.

7. The device package of claim 1 , wherein a sidewall of the die is in contact with a sidewall of the cavity formed through the die-side reinforcement layer.

8. The device package of claim 1 , wherein the die-side reinforcement layer has a thickness that is less than a thickness of the die.

9. The device package of claim 1 , wherein the first side of the die includes a die backside film (DBF), wherein a surface of the DBF is substantially coplanar with the first side of the die-side reinforcement layer.

10. The device package of claim 1 , wherein the die-side reinforcement layer comprises a plurality of layers stacked on each other.

11. The device package of claim 1 , wherein the build-up structure further comprises one or more intermediate glass cloth reinforcement layers.

12. The device package of claim 1 , further comprising a plurality of cavities formed through the die-side reinforcement layer, wherein one or more dies are positioned in each of the plurality of cavities.

Assignees

• Intel Corp

Inventors

• Rorane Digvijay A
• Chin Ian En Yoon
• Sobieski Daniel N

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W74/114

  by a substrate and the encapsulations · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title

• H10W95/00

  Packaging processes not covered by the other groups of this subclass · CPC title