Capacitive measurements of divots in semiconductor devices

Patent metadata

Field	Value
Publication number	US-9941179-B2
Application number	US-201514742917-A
Country	US
Kind code	B2
Filing date	Jun 18, 2015
Priority date	Jun 18, 2015
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

Approaches for characterizing a shallow trench isolation (STI) divot depth are provided. The approach includes measuring a first capacitance at a first region of a substrate where at least one first gate line crosses over a boundary junction between a STI region and an active region. The approach also includes measuring a second capacitance at a second region of the substrate where at least one second gate line crosses over the active region. The approach further includes calculating a capacitance associated with a divot at the first region based on a difference between the first capacitance at the first region and the second capacitance at the second region.

First claim

What is claimed is:

1. A method comprising:
measuring a first capacitance at a first region of a substrate where at least one first gate line crosses over a boundary junction between a shallow trench isolation (STI) region and an active region;
measuring a second capacitance at a second region of the substrate where at least one second gate line crosses over the active region; and
calculating a capacitance associated with a divot at the first region based on a difference between the first capacitance at the first region and the second capacitance at the second region.

2. The method of claim 1 , further comprising determining a depth of the divot based on the calculated divot capacitance.

3. The method of claim 1 , wherein the second region is where the at least one second gate line crosses over and completely covers only the active region of the substrate.

4. The method of claim 1 , further comprising adjusting the first capacitance for delta corrections in an actual length of the STI at the boundary junction with respect to a reference length of the STI.

5. The method of claim 1 , wherein the at least one first gate line comprises at least two first gate lines and the at least one second gate line comprises at least two second gate lines.

6. The method of claim 5 , wherein the at least two first gate lines are an outer pair of electrically connected gate lines which cross over the boundary junction between the STI region and the active region of the substrate.

7. The method of claim 5 , wherein the at least two second gate lines are an inner pair of electrically connected gate lines which crosses over the active region of the substrate.

8. The method of claim 1 , wherein a width of the active region of the substrate is greater than a length of the active region of the substrate.

9. The method of claim 1 , wherein the capacitance associated with the divot is calculated by equation 1 below:
C divot= C 1 −C 0−( L RX −L RX,target )* C 0/ L poly,  (equation 1)

wherein the first capacitance is measured as C 1 , half of the second capacitance is measured as C 0 , an adjustment of the first capacitance for delta corrections in an actual length of the STI at the boundary junction with respect to a reference length of the STI is (L RX −L RX, target ), and Lpoly is a length of a PC line.

10. A test structure comprising:
a first contact at a first region where at least one first gate line crosses over a boundary junction between a shallow trench isolation (STI) region and an active region of a substrate for measuring a first capacitance; and
a second contact at a second region where at least one second gate line crosses over the active region of the substrate for measuring a second capacitance.

11. The test structure of claim 10 , wherein the test structure is used for calculating a divot capacitance of a divot based on a difference between the first capacitance at the first contact and the second capacitance at the second contact.

12. The test structure of claim 11 , wherein the test structure is used for determining a depth of the divot based on the calculated divot capacitance.

13. The test structure of claim 11 , wherein the test structure is used for adjusting the first capacitance for delta corrections in an actual length of the STI at the boundary junction with respect to a reference length of the STI.

14. The test structure of claim 10 , wherein the second region is where the at least one second gate line crosses over and completely covers only the active region of the substrate.

15. A method comprising:
providing a first contact at a first region of a substrate where an outer pair of electrically connected gates crosses over a boundary junction between a shallow trench isolation (STI) region and an active region of a substrate;
providing a second contact at a second region of the substrate where an inner pair of electrically connected gates cross over the active region;
measuring a first capacitance at the first contact and a second capacitance at the second contact; and
calculating a divot capacitance of a divot location based on a difference between the first capacitance at the first contact and the second capacitance at the second contact.

16. The method of claim 15 , further comprising determining a depth of the divot based on the calculated divot capacitance.

17. The method of claim 15 , further comprising adjusting the first capacitance for delta corrections in an actual length of the STI at the boundary junction with respect to a reference length of the STI.

18. The method of claim 15 , wherein the second region is a region where the inner pair of electrically connected gates cross over and completely covers only the active region of the substrate.

19. The method of claim 15 , wherein the capacitance associated with the divot location is calculated by equation 2 below:
C divot= C 1 −C 0−( L RX −L RX,target )* C 0/ L poly,  (equation 2)

wherein the first capacitance is measured as C 1 , half of the second capacitance is measured as C 0 , an adjustment of the first capacitance for delta corrections in an actual length of the STI at the boundary junction with respect to a reference length of the STI is (L RX −L RX, target ), and Lpoly is a length of a PC line.

20. The method of claim 15 , wherein a width of the active region of the substrate is greater than a length of the active region of the substrate.

Assignees

• IBM
• Globalfoundries Inc

Inventors

• Logan Lyndon R
• Nowak Edward J
• Robison Robert R
• He Yan

Classifications

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10P74/277 Primary

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H01L22/14

  Electricity · mapped topic

• H01L22/34 Primary

  Electricity · mapped topic