PCIE traffic tracking hardware in a unified virtual memory system

Patent metadata

Field	Value
Publication number	US-9940286-B2
Application number	US-201314101246-A
Country	US
Kind code	B2
Filing date	Dec 9, 2013
Priority date	Mar 14, 2013
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

Techniques are disclosed for tracking memory page accesses in a unified virtual memory system. An access tracking unit detects a memory page access generated by a first processor for accessing a memory page in a memory system of a second processor. The access tracking unit determines whether a cache memory includes an entry for the memory page. If so, then the access tracking unit increments an associated access counter. Otherwise, the access tracking unit attempts to find an unused entry in the cache memory that is available for allocation. If so, then the access tracking unit associates the second entry with the memory page, and sets an access counter associated with the second entry to an initial value. Otherwise, the access tracking unit selects a valid entry in the cache memory; clears an associated valid bit; associates the entry with the memory page; and initializes an associated access counter.

First claim

What is claimed is:

1. A computer-implemented method for tracking memory page accesses in a unified virtual memory system, the method comprising:
based on determining that a set of memory pages is accessed by a first processor and a second processor, barring the set of memory pages from being tracked by access counters;
detecting a memory page access generated by the first processor for accessing a memory page, wherein the memory page resides in a memory system that is associated with the second processor;
determining that the memory page is not included in the set of memory pages that are barred from being tracked by the access counters;
determining whether a cache memory associated with the first processor includes a first entry corresponding to an address associated with the memory page; and
if the cache memory includes the first entry, then:
incrementing an access counter associated with the first entry that counts accesses of the memory page; or

if the cache memory does not include the first entry, then:
initializing a second entry in the cache memory to correspond to the memory page.

2. The method of claim 1 , wherein initializing a second entry in the cache memory to correspond to the memory page comprises:
determining whether an unused entry in the cache memory is available for allocation; and
if an unused entry in the cache memory is available for allocation; then
assigning the unused entry as the second entry;
associating the second entry with the memory page; and
setting an access counter associated with the second entry to an initial value; or

if an unused in the cache memory is not available for allocation; then
selecting a valid entry in the cache memory;
assigning the valid entry as the second entry;
clearing a valid bit included in the second entry;
associating the second entry with the memory page; and
setting an access counter associated with the second entry to an initial value.

3. The method of claim 2 , wherein determining whether an unused entry in the cache memory is available for allocation comprises determining whether a valid bit included in the second entry has been cleared.

4. The method of claim 2 , wherein associating the second entry with the memory page comprises:
storing a page number associated with the memory page in the second entry; and
setting a valid bit included in the second entry.

5. The method of claim 2 wherein selecting a valid entry in the cache memory comprises selecting from a set of all valid entries the entry having an access counter with the lowest value relative to the values of all other access counters associated with all other valid entries.

6. The method of claim 1 , further comprising:
receiving a command to initialize the cache memory; and
for each valid entry in the cache memory, clearing a valid bit included in the entry.

7. The method of claim 1 , further comprising:
receiving a command from at least one of the first processor and the second processor to read the access counters associated with one or more cache entries; and
transmitting data stored in one or more entries of the cache memory to the at least one of the first processor and the second processor.

8. The method of claim 1 , further comprising:
comparing the access counter associated with the first entry to a threshold value; and
indicating that the access counter is equal to the threshold value;
wherein the threshold value is based on a quantity of accesses that identifies the memory page as a candidate for migration to a memory system that is associated with the first processor.

9. The method of claim 1 , further comprising:
receiving a command to preset a third entry in the cache memory, wherein the command includes at least a portion of a second address;
storing the at least a portion of the second address in the third entry; and
setting a valid bit included in the third entry.

10. The method of claim 1 , wherein determining that the memory page is not included in a set of memory pages that are barred from being tracked by access counters comprises, after determining that the cache memory does not include the first entry, determining that a reference to the memory page does not appear on a list of physical memory pages that are barred from being added to the cache memory.

11. The method of claim 1 , wherein the first processor comprises a graphics processing unit, and the second processor comprises a central processing unit.

12. The method of claim 1 , wherein a bus coupling the first processor to the second processor comprises a peripheral component interconnect express (PCIe) bus.

13. The method of claim 1 , wherein the cache memory comprises a set associative memory.

14. A computer-implemented method for tracking memory page accesses in a unified virtual memory system, the method comprising:
detecting a memory page access generated by a first processor for accessing a memory page in a memory system that is associated with a second processor;
determining whether a cache memory associated with the first processor includes a first entry corresponding to an address associated with the memory page;
if the cache memory includes the first entry, then:
incrementing an access counter associated with the first entry that counts accesses of the memory page; or

if the cache memory does not include the first entry, then:
initializing a second entry in the cache memory to correspond to the memory page;

comparing the access counter associated with the first entry to a threshold value; and
indicating that the access counter is equal to the threshold value, wherein the threshold value is based on a quantity of accesses that identifies the memory page as a candidate for migration to a memory system that is associated with the first processor, wherein indicating that the access counter is equal to the threshold value comprises setting a flag associated with the first entry, and wherein either the first processor or the second processor identifies the memory page as a candidate for migration to a memory system that is associated with the first processor based on the flag.

15. A computer-implemented method for tracking memory page accesses in a unified virtual memory system, the method comprising:
detecting a memory page access generated by a first processor for accessing a memory page in a memory system that is associated with a second processor;
determining whether a cache memory associated with the first processor includes a first entry corresponding to an address associated with the memory page;
if the cache memory includes the first entry, then:
incrementing an access counter associated with the first entry that counts accesses of the memory page; or

if the cache memory does not include the first entry, then:
initializing a second entry in the cache memory to correspond to the memory page;

comparing the access counter associated with the first entry to a threshold value; and
indicating that the access counter is equal to the threshold value, wherein the threshold value is based on a quantity of accesses that identifies the memory page as a candidate for migration to a memory system that is associated with the first processor, wherein indicating that the access counter is equal to the threshold value comprises causing a trap condition, and wherein either the first processor or the second processor identifies the memory page as a candidate for migration to a memory system that is associated with the first processor in response to the trap condition.

16. A memory subsystem, comprising:
an access tracking mech

Assignees

• Nvidia Corp

Inventors

• Duluk Jr Jerome F
• Buschardt Cameron
• Deming James Leroy
• Fahs Brian
• Hairgrove Mark
• Mashey John

Classifications

• G06F12/0806

  Multiuser, multiprocessor or multiprocessing cache systems · CPC title

• G06F13/404 Primary

  with address mapping · CPC title

• G06F12/123

  with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list · CPC title

• G06F12/0864

  using pseudo-associative means, e.g. set-associative or hashing · CPC title

• G06F12/0875

  with dedicated cache, e.g. instruction or stack · CPC title