Immediate branch recode that handles aliasing

Patent metadata

Field	Value
Publication number	US-9940262-B2
Application number	US-201414491149-A
Country	US
Kind code	B2
Filing date	Sep 19, 2014
Priority date	Sep 19, 2014
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

A system and method for efficiently indicating branch target addresses. A semiconductor chip predecodes instructions of a computer program prior to installing the instructions in an instruction cache. In response to determining a particular instruction is a control flow instruction with a displacement relative to a program counter address (PC), the chip replaces a portion of the PC relative displacement in the particular instruction with a subset of a target address. The subset of the target address is an untranslated physical subset of the full target address. When the recoded particular instruction is fetched and decoded, the remaining portion of the PC relative displacement is added to a virtual portion of the PC used to fetch the particular instruction. The result is concatenated with the portion of the target address embedded in the fetched particular instruction to form a full target address.

First claim

What is claimed is:

1. A processor comprising:
an interface to a memory located external to a cache subsystem, wherein the interface is configured to send requests comprising physical fetch addresses to the memory for instructions;
a predecode unit; and
an instruction cache configured to store instructions; and
wherein the predecode unit is configured to:
receive instructions retrieved from the memory before the instructions are stored in the instruction cache; and
in response to determining a first instruction of the instructions received from the memory is a branch instruction with an immediate field storing a value that represents a displacement from a program counter (PC) used to fetch the branch instruction to a target of the branch instruction, recode the first instruction by:
replacing a lower portion of the displacement with a lower portion of a virtual address of the target of the branch instruction, wherein the lower portion of the displacement corresponds to a physical portion of the virtual address; and
retaining an upper portion of the displacement, wherein the upper portion of the displacement corresponds to a virtual portion of the virtual address; and
store the first instruction as recoded in the instruction cache prior to the first instruction as recoded being fetched during an instruction fetch pipeline stage for processing in later pipeline stages; and

a fetch unit configured to fetch instructions from the instruction cache for execution.

2. The processor as recited in claim 1 , wherein in response to determining the first instruction is not a branch instruction, the predecode unit is configured to store the first instruction in the instruction cache without performing said recode of the first instruction.

3. The processor as recited in claim 2 , wherein the predecode unit is further configured to generate a virtual address of the first instruction to send to the instruction cache, wherein the virtual address of the first instruction has at least two different virtual-to-physical mappings corresponding to at least two different processes.

4. The processor as recited in claim 3 , wherein an upper portion of each of the virtual address of the first instruction and the virtual address of the target of the branch instruction is based on which one of the at least two different processes is active.

5. The processor as recited in claim 1 , wherein prior to storing the first instruction in the instruction cache, the predecode unit is further configured to determine the lower portion of the virtual address of the target of the branch instruction by summing the lower portion of the displacement in the first instruction with the lower portion of a physical fetch address of the first instruction sent to the external memory.

6. The processor as recited in claim 5 , further comprising logic configured to determine the virtual address of the target of the branch by concatenating the upper portion of the virtual address of the target of the branch with the lower portion of the virtual address of the target of the branch stored in the first instruction.

7. The processor as recited in claim 5 , wherein the processor further comprises a next fetch predictor logic configured to access the next fetch predictor with the lower portion of the virtual address of the target of the branch stored in the first instruction while determining the upper portion of the virtual address of the target of the branch.

8. A method comprising:
sending requests comprising physical fetch addresses for instructions to a memory located external to a cache subsystem;
receiving at a predecode unit instructions retrieved from the memory before the instructions are stored in an instruction cache; and
in response to determining a first instruction of the instructions received from the memory is a branch instruction with an immediate field storing a value that represents a displacement from a program counter (PC) used to fetch the branch instruction to a target of the branch instruction, recoding the first instruction by the predecode unit by:
replacing a lower portion of the displacement with a lower portion of a virtual address of the target of the branch instruction, wherein the lower portion of the displacement corresponds to a physical portion of the virtual address; and
retaining an upper portion of the displacement, wherein the upper portion of the displacement corresponds to a virtual portion of the virtual address; and

storing the first instruction as recoded in the instruction cache prior to the first instruction as recoded being fetched during an instruction fetch pipeline stage for processing in later pipeline stages; and
fetching instructions by a fetch unit from the instruction cache for execution.

9. The method as recited in claim 8 , wherein in response to determining the first instruction is not a branch instruction, the method comprises storing the first instruction in the instruction cache without performing said recoding of the first instruction.

10. The method as recited in claim 9 , wherein the method further comprises generating a virtual fetch address of the first instruction to send to the instruction cache, wherein the virtual fetch address of the first instruction has at least two different virtual-to-physical mappings corresponding to at least two different processes.

11. The method as recited in claim 10 , wherein an upper portion of each of the virtual fetch address of the first instruction and the virtual address of the target of the branch instruction is based on which one of the at least two different processes is active.

12. The method as recited in claim 8 , wherein prior to storing the first instruction in the instruction cache, the method further comprises determining the lower portion of the virtual address of the target of the branch instruction by summing the lower portion of the displacement in the first instruction with the lower portion of a physical fetch address of the first instruction sent to the external memory.

13. The method as recited in claim 12 , wherein the method further comprises determining the virtual address of the target of the branch by concatenating the upper portion of the virtual address of the target of the branch with the lower portion of the virtual address of the target of the branch stored in the first instruction.

14. The method as recited in claim 12 , wherein the method further comprises accessing a next fetch predictor with the lower portion of the virtual address of the target of the branch stored in the first instruction while determining the upper portion of the virtual address of the target of the branch.

15. A non-transitory computer readable storage medium storing program instructions, wherein the program instructions are executable to:
send requests comprising physical fetch addresses for instructions to a memory located external to a cache subsystem;
receive instructions retrieved from the memory before the instructions are stored in an instruction cache; and
in response to determining a first instruction of the instructions received from the memory is a branch instruction with an immediate field storing a value that represents a displacement from a program counter (PC) used to fetch the branch instruction to a target of the branch instruction, recode the first instruction by:
replacing a lower portion of the displacement with a lower portion of a virtual address of the target of the branch instruction, wherein the lower portion of the displacement corresponds to a physical portion of the virtual address; and
retaining an upper portion of the displacemen

Assignees

• Apple Inc

Inventors

• Sundar Shyam
• Russo Richard F
• Hall Ronald P
• Blasco Conrado

Classifications

• G06F12/0875

  with dedicated cache, e.g. instruction or stack · CPC title

• G06F9/324

  using program counter relative addressing · CPC title

• G06F2212/452

  Instruction code · CPC title

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F2212/684

  TLB miss handling · CPC title