Utilization of register checkpointing mechanism with pointer swapping to resolve multithreading mis-speculations

Patent metadata

Field	Value
Publication number	US-9940138-B2
Application number	US-42076209-A
Country	US
Kind code	B2
Filing date	Apr 8, 2009
Priority date	Apr 8, 2009
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

Methods and apparatus are disclosed for using a register checkpointing mechanism to resolve multithreading mis-speculations. Valid architectural state is recovered and execution is rolled back. Some embodiments include memory to store checkpoint data. Multiple thread units concurrently execute threads. They execute a checkpoint mask instruction to initialize memory to store active checkpoint data including register contents and a checkpoint mask indicating the validity of stored register contents. As register contents change, threads execute checkpoint write instructions to store register contents and update the checkpoint mask. Threads also execute a recovery function instruction to store a pointer to a checkpoint recovery function, and in response to mis-speculation among the threads, branch to the checkpoint recovery function. Threads then execute one or more checkpoint read instructions to copy data from a valid checkpoint storage area into the registers necessary to recover a valid architectural state, from which execution may resume.

First claim

What is claimed is:

1. An apparatus, comprising:
a plurality of thread unit circuits to concurrently execute a plurality of threads, each of the plurality of thread unit circuits being capable of executing a checkpoint write instruction to update data stored in a memory storage area after execution of a checkpoint mask instruction; and
the memory storage area comprising an active checkpoint storage area and a most recent valid checkpoint storage area, wherein the active checkpoint storage area is to store, in response to the checkpoint write instruction, first data for the checkpoint write instruction encountered during execution of one of the plurality of threads, the first data corresponding to register content data being written by the checkpoint write instruction;
wherein the active checkpoint storage area is also to store second data for the checkpoint write instruction, the second data having a state indicative of a validity status of the register content data for the checkpoint write instruction, wherein an active checkpoint pointer, which points to the active checkpoint storage area, is to become a most recent valid checkpoint pointer, which points to the most recent valid checkpoint storage area, in response to a determination that all register contents corresponding to execution of multiple instances of the checkpoint write instruction by any of the plurality of thread unit circuits have been updated and all register contents corresponding to execution of the multiple instances of the checkpoint write instruction are indicated as completely valid by a checkpoint mask stored in the active checkpoint storage area.

2. The apparatus of claim 1 , wherein each of the plurality of thread unit circuits is further capable of executing the checkpoint mask instruction to initialize the state of said second data.

3. The apparatus of claim 2 , wherein executing the checkpoint mask instruction initializes the state of said second data for an active checkpoint.

4. The apparatus of claim 1 , wherein each of the plurality of thread unit circuits is further capable of executing a checkpoint read instruction to copy the first data from said memory storage area into a register.

5. The apparatus of claim 1 , wherein the memory storage area is also to store third data for a checkpoint recovery function.

6. The apparatus of claim 5 , wherein said third data corresponds to an instruction pointer for said checkpoint recovery function responsive to a recovery function instruction encountered during execution of said one of the plurality of threads.

7. A multi-threaded processor, comprising:
a plurality of thread unit circuits to concurrently execute a plurality of threads, each of the plurality of thread unit circuits being capable of executing a checkpoint write instruction to update data stored in a memory storage area after execution of a checkpoint mask instruction and each of the plurality of thread unit circuits being further capable of executing the checkpoint mask instruction; and
an execution unit of one of the plurality of thread unit circuits, responsive to the checkpoint mask instruction, to initialize the memory storage area comprising an active checkpoint storage area and a most recent valid checkpoint storage area, wherein the active checkpoint storage area is to store, in response to the checkpoint write instruction, at least first data and second data;
wherein said execution unit, responsive to the checkpoint write instruction, is to store the first data corresponding to register content data being written by the checkpoint write instruction, and store the second data having a state indicative of a validity status of the register content data for the checkpoint write instruction, and wherein an active checkpoint pointer, which points to the active checkpoint storage area, is to become a most recent valid checkpoint pointer, which points to the most recent valid checkpoint storage area, in response to a determination that all register contents corresponding to execution of multiple instances of the checkpoint write instruction by any of the plurality of thread unit circuits have been updated and all register contents corresponding to execution of the multiple instances of the checkpoint write instruction are indicated as completely valid by a checkpoint mask stored in the active checkpoint storage area.

8. The processor of claim 7 , wherein each of the plurality of thread unit circuits is further capable of executing a checkpoint read instruction to copy the first data from said memory storage area into a register.

9. The processor of claim 8 , wherein each of the plurality of thread unit circuits is further capable of executing a recovery function instruction to store, in said memory storage area, third data comprising an instruction pointer for a checkpoint recovery function.

10. A machine-implemented method for speculatively executing a plurality of threads, the method comprising:
executing a checkpoint mask instruction to initialize a memory storage area comprising an active checkpoint storage area and a most recent valid checkpoint storage area, wherein the active checkpoint storage area is to store at least first data and second data in response to a checkpoint write instruction capable of updating data stored in the memory storage area; and
executing the checkpoint write instruction to store the first data corresponding to register content data being written by the checkpoint write instruction and to store the second data having a state indicative of a validity status of the register content data for the checkpoint write instruction, wherein an active checkpoint pointer, which points to the active checkpoint storage area, is to become a most recent valid checkpoint pointer, which points to the most recent valid checkpoint storage area, in response to a determination that all register contents corresponding to execution of multiple instances of the checkpoint write instruction by any of a plurality of thread unit circuits have been updated and all register contents corresponding to execution of the multiple instances of the checkpoint write instruction are indicated as completely valid by a checkpoint mask stored in the active checkpoint storage area.

11. The method of claim 10 , further comprising:
executing a recovery function instruction to store, in said memory storage area, third data comprising an instruction pointer for a checkpoint recovery function.

12. The method of claim 11 , further comprising:
executing a checkpoint read instruction to copy the first data from said memory storage area into a register.

13. The method of claim 12 , wherein executing said checkpoint read instruction is a result of branching to a location specified by the instruction pointer for said checkpoint recovery function in response to a mis-speculation among the plurality of threads.

14. A machine-implemented method for mis-speculation recovery among a plurality of threads, the method comprising:
executing a recovery function instruction to store, in a memory storage area comprising an active checkpoint storage area and a most recent valid checkpoint storage area, prior to a checkpoint write instruction capable of updating data stored in the memory storage area after execution of a checkpoint mask instruction, first data comprising an instruction pointer for a checkpoint recovery function;
branching to a location specified by the instruction pointer for said checkpoint recovery function in response to a mis-speculation among the plurality of threads; and
executing a checkpoint read instruction to copy second data from said memory storage area into a

Assignees

• Lopez Pedro
• Madriles Carlos
• Martinez Alejandro
• Martinez Raul
• Codina Josep M
• Codina Enric Gibert
• Latorre Fernando
• Gonzalez Antonio
• Intel Corp

Inventors

• Lopez Pedro
• Madriles Carlos
• Martinez Alejandro
• Martinez Raul
• Codina Josep M
• Codina Enric Gibert
• Latorre Fernando
• Gonzalez Antonio

Classifications

• G06F9/3842

  Speculative instruction execution · CPC title

• G06F9/3863 Primary

  using multiple copies of the architectural state, e.g. shadow registers · CPC title

• G06F11/1402

  Saving, restoring, recovering or retrying · CPC title

• G06F9/3851

  from multiple instruction streams, e.g. multistreaming · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title