Low power tunable reference current generator

Patent metadata

Field	Value
Publication number	US-9939826-B2
Application number	US-201214342177-A
Country	US
Kind code	B2
Filing date	Jun 29, 2012
Priority date	Jul 3, 2011
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

An improved reference current generator for use in an integrated circuit. A voltage difference generator generates two voltages that are separated by a relatively small electrical potential. The two closely separated voltages are applied across a resistive element with relatively large impedance value resulting in a small and stable reference current. The stable reference current is mirrored and, if desired, amplified for use on the integrated circuit. A driver selectively drives state information off chip for assisting in post-silicon correction of unwanted sensitivities. A configuration memory stores values used to adjust effective device widths and lengths for correcting unwanted sensitivities.

First claim

What we claim is:

1. A circuit for developing a reference current, the circuit comprising:
a voltage difference generator adapted to:
develop a first voltage;
develop a second voltage; and
selectively develop a first state voltage as a function of said first and second voltages and a first control signal;

a resistive element adapted to:
receive said first voltage;
receive said second voltage;
develop a first reference current as a function of said first voltage and said second voltage; and
selectively develop a first state current as a function of said first and second voltages and a second control signal;

a current mirror adapted to:
receive said first reference current;
develop an output reference current as a function of said first reference current; and
selectively develop a second state current as a function of said first reference current and a third control signal; and

a configuration memory adapted to develop a selected one of:
said first control signal;
said second control signal; and
said third control signal.

2. The circuit of claim 1 wherein the circuit for developing a current reference is further characterized as comprising a driver adapted to receive a selected one of:
said first state voltage;
said first state current; and
said second state current.

3. The circuit of claim 1 wherein said first voltage and said second voltage are further characterized as being closely separated.

4. The circuit of claim 1 wherein said voltage difference generator is further characterized as comprising a plurality of transistor devices operating in a sub-threshold region.

5. The circuit of claim 4 wherein said plurality of transistor devices is further characterized as a plurality of a selected one of N-channel transistors and P-Channel transistors.

6. The circuit of claim 1 wherein said resistive element is further characterized as a plurality of transistor devices operating in a sub-threshold region.

7. The circuit of claim 6 wherein said plurality of transistor devices is further characterized as comprising a selected one of N-channel transistors and P-channel transistors.

8. The circuit of claim 1 wherein said current mirror-multiplier is further characterized as a plurality of transistor devices operating in a sub-threshold region.

9. The circuit of claim 8 wherein said plurality of transistor devices is further characterized as comprising a selected one of N-channel transistors and P-channel transistors.

10. The circuit of claim 1 wherein at least a selected one of said voltage difference generator, said resistive element, and said current mirror are adapted to be tuned to effect at least a selected one of minimum temperature sensitivity, proportional-to-absolute temperature characteristic, and complementary-to-absolute temperature characteristic.

11. The circuit of claim 1 wherein:
the voltage difference generator is further characterized as developing said first and second voltages as a function of a fourth control signal; and
the configuration memory is further characterized as developing said fourth control signal.

12. The circuit of claim 1 wherein:
the resistive element is further characterized as developing said first reference current as a function of said first and second voltages and a fifth control signal; and
the configuration memory is further characterized as developing said fifth control signal.

13. The circuit of claim 1 wherein:
the current mirror is further characterized as developing said output reference current as a function of said first reference current and a sixth control signal; and
the configuration memory is further characterized as developing said sixth control signal.

Assignees

• Hanson Scott
• Ifesinachukwu Kenneth Gozie
• Kanji Ajaykumar A
• Ambiq Micro Inc

Inventors

• Hanson Scott
• Ifesinachukwu Kenneth Gozie
• Kanji Ajaykumar A

Classifications

• G05F3/08

  wherein the variable is DC · CPC title

• G06F1/08

  Clock generators with changeable or programmable clock frequency · CPC title

• G05F3/262

  using field-effect transistors only · CPC title

• G06F1/10

  Distribution of clock signals {, e.g. skew} · CPC title

• H03K21/023

  comprising pulse shaping or differentiating circuits · CPC title