Capacitive micromachined ultrasonic transducer (CMUT) forming

US9937528B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9937528-B2
Application numberUS-201615095264-A
CountryUS
Kind codeB2
Filing dateApr 11, 2016
Priority dateFeb 27, 2013
Publication dateApr 10, 2018
Grant dateApr 10, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A Capacitive Micromachined Ultrasonic Transducer (CMUT) device including at least one CMUT element with at least one CMUT cell is formed. A patterned dielectric layer thereon including a thick and a thin dielectric region is formed on a top side of a single crystal material substrate. A second substrate is bonded to the thick dielectric region to provide at least one sealed micro-electro-mechanical system (MEMS) cavity. The second substrate is thinned to reduce a thickness of said second substrate to provide a membrane layer. The membrane layer is etched to form a movable membrane over said MEMS cavity and to remove said membrane layer over said top side substrate contact area. The thin dielectric region is removed from over said top side substrate contact area. A top side metal layer is formed including a trace portion coupling said top side substrate contact area to said movable membrane. From a bottom side surface of said first substrate, etching is performed to open an isolation trench around said single crystal material to form a through-substrate via (TSV) plug of said single crystal material at least under said top side substrate contact area which is electrically isolated from surrounding regions of said single crystal material.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of forming a capacitive micromachined ultrasonic transducer (CMUT) device including at least one CMUT element with at least one CMUT cell, comprising: forming a patterned dielectric layer including a thick dielectric region and a thin dielectric region on a top side of a first substrate including a thin dielectric region over a top side substrate contact area on a top side surface of said first substrate, wherein said first substrate comprising a single crystal material, and wherein said single crystal material has a resistivity less than (<) 0.1 ohm-cm; bonding a second substrate to said thick dielectric region to provide at least one sealed micro-electro-mechanical system (MEMS) cavity; thinning said second substrate to reduce a thickness of said second substrate to provide a membrane layer; etching said membrane layer to form a movable membrane over said MEMS cavity, and to remove said membrane layer over said top side substrate contact area; removing said thin dielectric region from over said top side substrate contact area; forming a top side metal layer over said top side substrate contact area and over said movable membrane including a trace portion coupling said top side substrate contact area to said movable membrane, and from a bottom side surface of said first substrate, etching to open an isolation trench around said single crystal material to form a through-substrate via (TSV) plug of said single crystal material at least under said top side substrate contact area which is electrically isolated from surrounding regions of said single crystal material. 2. The method of claim 1 , wherein said forming said patterned dielectric layer comprises a high pressure oxidation (HiPOx) growth process. 3. The method of claim 1 , further comprising forming a patterned metal layer on said bottom side surface of said first substrate including a first patterned layer portion contacting a bottom side of said TSV and a second patterned layer portion contacting said bottom side of said first substrate lateral to said TSV. 4. The method of claim 1 , further comprising filling said isolation trench with a solid dielectric material. 5. The method of claim 1 , wherein said single crystal material comprises single crystal silicon. 6. The method of claim 1 , wherein said CMUT device includes a plurality of said CMUT elements, wherein each of said plurality of said CMUT elements include a plurality of said CMUT cells, wherein all of said movable membranes in each of said plurality of said CMUT elements are connected together so that said movable membranes in each of said plurality of said CMUT elements are all addressable by contacting said TSV. 7. The method of claim 1 , further comprising depositing at least one dielectric passivation layer on a top of said CMUT device including over said top side metal layer. 8. The method of claim 1 , wherein said bonding comprises vacuum fusion bonding. 9. The method of claim 1 , wherein said bonding said second substrate comprises bonding said membrane layer of a semiconductor on insulator (SOI) substrate having a handle and a buried dielectric layer in between said handle and said membrane layer, and said thinning said second substrate comprises removing said handle then removing said buried dielectric layer. 10. A method of forming a capacitive micromachined ultrasonic transducer (CMUT) device including at least one CMUT element with at least one CMUT cell, comprising: forming a patterned dielectric layer including a thick dielectric region and a thin dielectric region on a top side of a first substrate including a thin dielectric region over a top side substrate contact area on a top side surface of said first substrate, wherein said first substrate comprising a single crystal material, and wherein said single crystal material has a resistivity less than (<) 0.1 ohm-cm; vacuum fusion bonding a membrane layer of a semiconductor on insulator (SOI) substrate having a buried dielectric layer and a handle opposite said membrane layer to said thick dielectric region to provide at least one sealed micro-electro-mechanical system (MEMS) cavity; removing said handle of said SOI substrate; etching said membrane layer to form a movable membrane over said MEMS cavity, and to remove said membrane layer over said top side substrate contact area; removing said thin dielectric region from over said top side substrate contact area; forming a top side metal layer over said top side substrate contact area and over said movable membrane including a trace portion coupling said top side substrate contact area to said movable membrane, and from a bottom side surface of said first substrate, etching to open an isolation trench around said single crystal material to form a through-substrate via (TSV) plug of said single crystal material at least under said top side substrate contact area which is electrically isolated from surrounding regions of said single crystal material. 11. The method of claim 10 , wherein said single crystal material comprises single crystal silicon.

Assignees

Inventors

Classifications

  • Etching · CPC title

  • Medical, dental · CPC title

  • Diaphragms, i.e. structures separating two media that can control the passage from one medium to another; Membranes, i.e. diaphragms with filtering function · CPC title

  • Concave hole or via · CPC title

  • using semiconductor materials · CPC title

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What does patent US9937528B2 cover?
A Capacitive Micromachined Ultrasonic Transducer (CMUT) device including at least one CMUT element with at least one CMUT cell is formed. A patterned dielectric layer thereon including a thick and a thin dielectric region is formed on a top side of a single crystal material substrate. A second substrate is bonded to the thick dielectric region to provide at least one sealed micro-electro-mechan…
Who is the assignee on this patent?
Texas Instruments Inc
What technology area does this patent fall under?
Primary CPC classification B06B1/0292. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Tue Apr 10 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).