Internal spacers for nanowire transistors and method of fabrication thereof

Patent metadata

Field	Value
Publication number	US-9935205-B2
Application number	US-201615335269-A
Country	US
Kind code	B2
Filing date	Oct 26, 2016
Priority date	Oct 3, 2013
Publication date	Apr 3, 2018
Grant date	Apr 3, 2018

Abstract

A nanowire transistor of the present description may be produced with internal spacers formed by using sacrificial spacers during the fabrication thereof. Once the nanowire transistor is formed, the sacrificial spacers, which are position between the transistor gate and the source and drains (respectively), may be removed. The sacrificial material between channel nanowires of the nanowire transistor may then be removed and a dielectric material may be deposited to fill the spaces between the channel nanowires. The dielectric material not between the channel nanowires may be removed to form the internal spacers. External spacers, which are position between the transistor gate and the source and drains (respectively), may then be formed adjacent the internal spacers and transistor channel nanowires.

First claim

What is claimed is:

1. A microelectronic structure having:
a fin structure, having a plurality of channel nanowires, disposed on a substrate, wherein channel nanowires of the plurality of channel nanowires are in a stacked configuration relative to the substrate;
a gate structure abutting a portion of the fin structure, wherein the gate structure comprises a gate dielectric surrounding each of the plurality of the channel nanowires in the fin structure and a gate electrode abutting the gate dielectric; and
a dielectric material spacer adjacent one end of the gate electrode, wherein the dielectric material spacer abuts a portion of the fin structure that comprises the plurality of channel nanowires, wherein a portion of the dielectric material spacer is disposed between and contacts each channel nanowire of the plurality of channel nanowires, and wherein the dielectric material spacer comprises a single dielectric material structure.

2. The microelectronic structure of claim 1 , wherein the dielectric material spacer comprises a low-k dielectric material.

3. The microelectronic structure of claim 1 , wherein the channel nanowires comprise silicon germanium.

4. The microelectronic structure of claim 1 , wherein the channel nanowires comprise silicon.

5. The microelectronic structure of claim 1 , further comprising one of a source and a drain abutting one end of the fin structure and the dielectric material spacer.

6. The microelectronic structure of claim 1 , further comprising a second dielectric material spacer adjacent another end of the gate electrode, wherein the second dielectric material spacer abuts a portion of the fin structure that comprises the plurality of channel nanowires, wherein a portion of the second dielectric material spacer is disposed between and contacts each channel nanowire of the plurality of channel nanowires, and wherein the second dielectric material spacer comprises a single dielectric material structure.

7. The microelectronic structure of claim 6 , further comprising one of a source and a drain abutting another end of the fin structure and the second dielectric material spacer.

8. The microelectronic structure of claim 6 , wherein the second dielectric material spacer comprises a low-k dielectric material.

Assignees

• Intel Corp

Inventors

• Kim Seiyon
• Simon Daniel A
• Rahhal-Orabi Nadia M
• Lim Chul-Hyun
• Kuhn Kelin J

Classifications

• H10P14/3462

  Nanowires · CPC title

• H01L27/092

  Electricity · mapped topic

• H01L29/78618

  Electricity · mapped topic

• H01L21/823807

  Electricity · mapped topic

• H01L29/6653

  Electricity · mapped topic