Composite wafer semiconductor devices using offset via arrangements and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-9780136-B2
Application number	US-201615273029-A
Country	US
Kind code	B2
Filing date	Sep 22, 2016
Priority date	Sep 24, 2015
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

A device includes a first integrated circuit substrate including a plurality of first metal layers interconnected by first vias and a second integrated circuit substrate on the first integrated circuit substrate and including second metal layers interconnected by second vias. An insulation layer is disposed between the first and second substrates and a connection region is disposed in the insulation layer and electrically connects a first one of the first metal layers to a first one of the second metal layers. The device further includes a bonding pad on the second substrate and a through via extending from the bonding pad and into the second to contact a second one of the second metal layers. The through via is positioned so as to not overlap at least one of the first vias, the second vias and the connection region. Methods of fabricating such device are also described.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first sub chip including a first substrate, first metal layers on the first substrate, and a first via group between the first metal layers, the first via group comprising a plurality of vias electrically interconnecting the first metal layers;
a second sub chip including a second substrate, second metal layers on the second substrate, and a second via group between the second metal layers, the second via group comprising a plurality of vias electrically interconnecting the second metal layers;
a connection layer disposed between the first and second sub chips and including an insulating layer interposed between the first and second sub chips and a connection region disposed in the insulating layer and electrically connecting the first metal layers to the second metal layers; and
a through via passing through the second substrate and electrically connected to the second metal layers,
wherein at least one of the first via group, the second via group, and the connection region is laterally spaced apart from the through via.

2. The device of claim 1 , further comprising an input/output (I/O) pad on a first surface of the second substrate, wherein the through via is electrically connected to the input/output pad and wherein the second metal layers are disposed on a second surface of the second substrate on an opposite side of the second substrate from the first surface.

3. The device of claim 1 , wherein the connection region is laterally spaced apart from the through via.

4. The device of claim 3 , wherein the first via group and the second via group substantially overlap.

5. The device of claim 3 , wherein at least one of the first via group or the second via group substantially overlaps the connection region.

6. The device of claim 3 , wherein at least one of the first via group or the second via group substantially overlaps the through via.

7. The device of claim 3 , wherein the first via group, the second via group, the connection region, and the through via are laterally spaced apart.

8. The device of claim 1 , wherein the first and second sub chips form a semiconductor chip having first and second surfaces on opposite sides of the semiconductor chip, and wherein the first and second substrates are disposed adjacent respective ones of the first and second surfaces.

9. The device of claim 1 , wherein the connection region comprises a first connection pattern adjacent the first sub chip and a second connection pattern adjacent the second sub chip and in direct contact with the first connection pattern.

10. A semiconductor device, comprising:
a first sub chip including a first substrate and first metal layers on the first substrate;
a second sub chip including a second substrate and second metal layers on the second substrate;
a connection region disposed between the first and second sub chips and electrically connecting the first metal layers to the second metal layers;
a through via penetrating the second substrate and electrically connected to the second metal layers; and
an input/output pad electrically connected to the second metal layers through the through via,
wherein the second substrate comprises a first surface, and a second surface on a side of the second substrate opposite the first surface,
wherein the input/output pad is disposed on the first surface, and
wherein the second metal layers are disposed on the second surface,
wherein the first metal layers, the connection region, and the second metal layers are interposed between the first substrate and the second substrate, and
wherein the connection region is laterally spaced apart from the through via.

11. A device comprising:
a first integrated circuit substrate comprising a plurality of first metal layers interconnected by first vias;
a second integrated circuit substrate on the first integrated circuit substrate and comprising second metal layers interconnected by second vias; and
an insulation layer disposed between the first and second integrated circuit substrates;
a connection region in the insulation layer and electrically connecting a first one of the first metal layers to a first one of the second metal layers;
a bonding pad on the second integrated circuit substrate; and
a through via extending from the bonding pad and into the second integrated circuit substrate to contact a second one of the second metal layers, the through via positioned so as to not overlap at least one of the first vias, the second vias and the connection region.

12. The device of claim 11 , wherein the through via does not overlap any of the first and second vias and wherein none of the first vias overlap any of the second vias.

13. The device of claim 12 , wherein none of the first vias overlaps the connection region and wherein the connection region does not overlap any of the second vias.

14. The device of claim 11 , wherein through via does not overlap any of the first and second vias and wherein at least one of the first vias overlaps at least one of the second vias.

15. The device of claim 14 , wherein none of the first vias overlaps the connection region and wherein the connection region does not overlap any of the second vias.

16. The device of claim 14 , wherein at least one of the first vias overlaps the connection region and wherein the connection region overlaps at least one of the second vias.

17. The device of claim 11 , wherein the through via overlaps at least one of the first vias and wherein none of the first vias overlaps the connection region.

18. The device of claim 17 , wherein the through via overlaps the connection region.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kwon Doowon

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W72/07354

  changes in dispositions · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title