Charged-particle-beam patterning without resist

Patent metadata

Field	Value
Publication number	US-9934969-B2
Application number	US-201414304691-A
Country	US
Kind code	B2
Filing date	Jun 13, 2014
Priority date	Jan 31, 2014
Publication date	Apr 3, 2018
Grant date	Apr 3, 2018

Abstract

A process for fabricating an integrated circuit is provided. The process includes providing a substrate, forming a hard mask upon the substrate by one of atomic-layer deposition and molecular-layer deposition, and exposing the hard mask to a charged particle from one or more charged particle beams to pattern a gap in the hard mask. In the alternative, the process includes exposing the hard mask to a charged particle from one or more charged-particle beams to pattern a structure on the hard mask.

First claim

What is claimed is:

1. A process for fabricating an integrated circuit, comprising:
forming a hard mask upon a substrate by one of atomic-layer deposition and molecular-layer deposition;
flowing a precursor gas over the hard mask; and
after flowing the precursor gas over the hard mask, exposing the hard mask and the precursor gas to a charged particle from one or more charged-particle beams, wherein the charged particle and the precursor gas deposit a structure on the hard mask, wherein molecules of the precursor gas absorbed on the hard mask are dissociated into volatile and non-volatile components under the influence of the one or more charged-particle beams, wherein the volatile components of the precursor gas adhere to the hard mask in an area exposed to the charged particle, and wherein an entirety of a bottommost surface of the structure is in physical contact with a material of the hard mask.

2. The process of claim 1 , wherein the charged particle is one of helium, neon, argon, silicon, beryllium, gold, and gallium.

3. The process of claim 1 , wherein a thickness of the hard mask is less than about five nanometers.

4. The process of claim 1 , wherein the one or more charged-particle beams have a beam diameter of less than about one nanometer.

5. The process of claim 1 , wherein the precursor gas contains one of TEOS, Styrene, TMCTS, Naphthalene, Al, Au, amorphous carbon, diamond, Co, Cr, Cu, Fe, GaAs, GaN, Ge, Mo, Nb, Ni, Os, Pd, CpPtMe 3 , MeCpPtMe 3 , a compound containing Pt, Rh, Ru, Re, Si, Si 3 N 4 , SiOx, TiOx, W, and a combination thereof.

6. The process of claim 1 , wherein the structure is deposited over a portion of the hard mask exposed to the one or more charged-particle beams.

7. The process of claim 1 , wherein the structure forms an additional hard mask over the hard mask.

8. A process for fabricating an integrated circuit, comprising:
forming a first hard mask upon a semiconductor substrate by one of atomic-layer deposition and molecular-layer deposition;
flowing a precursor gas over an entire surface of the first hard mask; and
after flowing the precursor gas over the entire surface of the first hard mask, directing one or more charged-particle beams at the first hard mask to pattern the first hard mask, wherein the precursor gas undergoes a dissociation reaction into volatile and non-volatile components under the influence of the one or more charged-particle beams and forms a second hard mask on the first hard mask, wherein the volatile components adhere to the first hard mask in an area to which the charged-particle beams are directed to form the second hard mask, wherein the second hard mask is in physical contact with the first hard mask, and wherein an interface between the first hard mask and the second hard mask is at least as wide as the second hard mask.

9. The process of claim 8 , wherein the one or more charged-particle beams comprises helium, neon, argon, silicon, beryllium, gold, or gallium.

10. The process of claim 8 , wherein the one or more charged-particle beams have a beam diameter of less than about one nanometer.

11. The process of claim 8 , wherein the first hard mask is in physical contact with the semiconductor substrate, and wherein a thickness of the first hard mask is less than about five nanometers.

12. The process of claim 8 , wherein the precursor gas contains one of TEOS, Styrene, TMCTS, Naphthalene, Al, Au, amorphous carbon, diamond, Co, Cr, Cu, Fe, GaAs, GaN, Ge, Mo, Nb, Ni, Os, Pd, CpPtMe 3 , MeCpPtMe 3 , a compound containing Pt, Rh, Ru, Re, Si, Si 3 N 4 , SiOx, TiOx, W, and a combination thereof.

13. The process of claim 8 , wherein the second hard mask is formed of Pt, Co, or SiO 2 .

14. The process of claim 8 , wherein the second hard mask is formed over a portion of the first hard mask exposed to the one or more charged-particle beams.

15. A process for fabricating an integrated circuit, comprising:
forming a hard mask on a substrate by one of atomic-layer deposition and molecular-layer deposition, the hard mask having a first sidewall and a second sidewall opposite the first sidewall, wherein a continuous material of the hard mask extends between the first sidewall and the second sidewall;
flowing a precursor gas over an entire surface of the hard mask; and
after flowing the precursor gas over the entire surface of the hard mask, exposing a portion of the hard mask to one or more charged-particle beams carrying a charged particle, the charged particle patterning the hard mask, wherein the charged particle causes the precursor gas to dissociate into volatile components and non-volatile components, wherein the volatile components adhere to the portion of the hard mask exposed to the one or more charged-particle beams, wherein the charged particle and the precursor gas deposit a structure on the portion of the hard mask, wherein the structure is fully formed immediately after exposing the hard mask to the one or more charged-particle beams, wherein the structure is in physical contact with the continuous material of the hard mask, wherein at least one sidewall of the structure is interposed between the first sidewall and the second sidewall of the hard mask, and wherein at least a portion of a top surface of the continuous material of the hard mask remains exposed after depositing the structure on the hard mask.

16. The process of claim 15 , wherein the charged particle is one of helium, neon, argon, silicon, beryllium, gold, and gallium.

17. The process of claim 15 , wherein the precursor gas contains one of TEOS, Styrene, TMCTS, Naphthalene, Al, Au, amorphous carbon, diamond, Co, Cr, Cu, Fe, GaAs, GaN, Ge, Mo, Nb, Ni, Os, Pd, CpPtMe 3 , MeCpPtMe 3 , a compound containing Pt, Rh, Ru, Re, Si, Si 3 N 4 , SiOx, TiOx, W, and a combination thereof.

18. The process of claim 15 , wherein the structure forms an additional hard mask over the hard mask.

19. The process of claim 15 , wherein the one or more charged-particle beams have a beam diameter of less than about one nanometer.

20. The process of claim 15 , wherein the hard mask is in physical contact with the substrate, and wherein a thickness of the hard mask is less than about five nanometers.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Univ Nat Taiwan

Inventors

• Tsai Kuen-Yu
• Chen Miin-Jang
• Pan Samuel C

Classifications

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P14/6539

  by exposure to corpuscular radiation, e.g. exposure to electrons, alpha-particles, protons or ions · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10P14/63

  characterised by the formation processes · CPC title

• H10P76/4085 Primary

  characterised by the processes involved to create the masks · CPC title