Projection patterning with exposure mask

Patent metadata

Field	Value
Publication number	US-9570301-B2
Application number	US-201414290742-A
Country	US
Kind code	B2
Filing date	May 29, 2014
Priority date	May 29, 2014
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

A process for fabricating an integrated circuit is provided. The process includes providing a substrate and forming a hard mask on the substrate. The hard mask may be formed by atomic-layer deposition (ALD) or molecular-layer deposition (MLD). The process also includes disposing an exposure mask over the hard mask and exposing the exposure mask to a patterning particle to pattern a gap in the hard mask. The patterning particle may be, for example, a photon or a charged particle.

First claim

What is claimed is:

1. A process for fabricating an integrated circuit, comprising:
providing a substrate;
forming a hard mask on the substrate by one of atomic-layer deposition and molecular-layer deposition;
disposing an exposure mask over the hard mask; and
exposing the exposure mask to a patterning particle to pattern a gap in the hard mask, the exposing removing at least a portion of the hard mask.

2. The process of claim 1 , wherein the gap in the hard mask is patterned by sputtering and using an energy of the patterning particle.

3. The process of claim 1 , wherein the gap in the hard mask is patterned by etching with a precursor.

4. The process of claim 1 , wherein the patterning particle is a photon.

5. The process of claim 1 , wherein the patterning particle is one of a deep ultraviolet photon, an extreme ultraviolet photon, and an x-ray photon.

6. The process of claim 1 , wherein the patterning particle is a charged particle.

7. The process of claim 1 , wherein the patterning particle is one of helium, neon, argon, silicon, beryllium, gold, and gallium.

8. The process of claim 1 , wherein a thickness of the hard mask is less than about five nanometers.

9. A process for fabricating an integrated circuit, comprising:
providing a substrate;
forming a hard mask on the substrate by one of atomic-layer deposition and molecular-layer deposition; and
patterning the hard mask in accordance with an exposure mask, the patterning exposing a portion of the hard mask to a patterning particle.

10. The process of claim 9 , wherein the patterning particle is one of a deep ultraviolet photon, an extreme ultraviolet photon, and an x-ray photon.

11. The process of claim 9 , wherein the patterning particle is one of helium, neon, argon, and gallium.

12. The process of claim 9 , wherein the patterning particle forms a gap in the hard mask by sputtering.

13. The process of claim 9 , wherein the patterning particle forms a gap in the hard mask by etching with a precursor gas, the precursor gas comprising one of XeF 2 , SF 6 , nitrosyl chloride (NOCl), chlorine (Cl 2 ), chlorine trifluoride (ClF 3 ), oxygen (O 2 ), water (H 2 O), air, and a combination thereof.

14. The process of claim 9 , wherein a medium between the exposure mask and the hard mask is a vacuum, air, or water.

15. A process for fabricating an integrated circuit, comprising:
providing a substrate;
forming a hard mask on the substrate by one of atomic-layer deposition and molecular-layer deposition;
disposing an exposure mask over the hard mask;
flowing a precursor gas over an entire surface of the hard mask; and
exposing a portion of the hard mask to a patterning particle in accordance with the exposure mask to pattern the hard mask, wherein the patterning particle and the precursor gas form a structure on the hard mask.

16. The process of claim 15 , wherein the patterning particle is one of a deep ultraviolet photon, an extreme ultraviolet photon, and an x-ray photon.

17. The process of claim 15 , wherein the patterning particle is one of helium, neon, argon, and gallium.

18. The process of claim 15 , wherein the precursor gas contains one of TEOS, Styrene, TMCTS, Naphthalene, Al, Au, amorphous carbon, diamond, Co, Cr, Cu, Fe, GaAs, GaN, Ge, Mo, Nb, Ni, Os, Pd, CpPtMe 3 , MeCpPtMe 3 , a compound containing Pt, Rh, Ru, Re, Si, Si 3 N 4 , SiOx, TiOx, W, and a combination thereof.

19. The process of claim 15 , wherein the exposure mask has a plurality of apertures extending therethrough.

20. The process of claim 19 , wherein the structure is disposed on the hard mask below one of the plurality of apertures.

Assignees

• Univ Nat Taiwan
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tsai Kuen-Yu
• Chen Miin-Jang
• Lee Si-Chen

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P76/2049

  Ion beam lithography processes · CPC title

• H10P76/2047

  X-ray beam lithography processes · CPC title

• H10P76/2041 Primary

  Photolithographic processes · CPC title

• H10P50/283

  by chemical means · CPC title