Method for operating memory controller and devices having the same

Patent metadata

Field	Value
Publication number	US-9037950-B2
Application number	US-201213727194-A
Country	US
Kind code	B2
Filing date	Dec 26, 2012
Priority date	Apr 9, 2012
Publication date	May 19, 2015
Grant date	May 19, 2015

Abstract

A memory controller and an operating method of the memory controller are provided. The operating method includes: performing error correction on data, including a plurality of chunks, in a unit of a chunk; determining if a coefficient of each term of which a degree is equal to or greater than a degree of a reference-degree term, in an error location polynomial for a last chunk among the plurality of chunks, is all zero; and controlling an output time of an error-corrected first chunk based on a result of the determining.

First claim

What is claimed is:

1. A method for operating a memory controller comprising:
performing error correction on data, comprising a plurality of chunks, in a unit of a chunk;
determining whether a coefficient of each term of which a degree is equal to or greater than a degree of a reference-degree term, in an error location polynomial for a last chunk among the plurality of chunks, is all zero; and
controlling an output time of a first chunk, which is error-corrected, among the plurality of chunks, from the memory controller, based on a result of the determining,
wherein the controlling the output time comprises:
outputting the error-corrected first chunk before error correction on the last chunk is completed if it is determined that the coefficient of the each term is all zero; and
performing error correction on the last chunk before outputting the error-corrected first chunk if it is determined that a coefficient of any term of which a degree is equal to or greater than the degree of the reference-degree term, in the error location polynomial for the last chunk among the plurality of chunks, is not zero.

2. The method of claim 1 , wherein the controlling the output time comprises outputting the error-corrected first chunk while a root of the error location polynomial for the last chunk is calculated or while error correction on the last chunk is performed using a plurality of error locations corresponding to the calculated root if it is determined that the coefficient of the each term is all zero.

3. A memory controller comprising:
a memory interface through which data is input; and
an error correction code (ECC) block which controls:
to perform error correction on the data, comprising a plurality of chunks in a unit of a chunk;
to determine whether a coefficient of each term of which a degree is equal to or greater than a degree of a reference-degree term, in an error location polynomial for a last chunk among the plurality of chunks, is all zero; and
to determine an output time of a first chunk, which is error-corrected, among the plurality of chunks, from the memory controller, based on a result of the determining whether the coefficient of the each term is all zero,

wherein the ECC block controls:
to output the error-corrected first chunk before error correction on the last chunk is completed if it is determined that the coefficient of each term is all zero; and
to perform error correction on the last chunk before outputting the error-corrected first chunk if it is determined that a coefficient of any term of which a degree is equal to or greater than the degree of the reference-degree term, is not zero.

4. The memory controller of claim 3 , wherein the ECC block controls to output the error-corrected first chunk while a root of the error location polynomial for the last chunk is calculated or while error correction on the last chunk is performed using a plurality of error locations corresponding to the calculated root, if it is determined that the coefficient of the each term is all zero.

5. The memory controller of claim 3 , wherein the error correction code block calculates a syndrome value for each of the plurality of chunks, calculates an error location polynomial for the each chunk from the calculated syndrome value, calculates a root of the calculated error location polynomial for the each chunk, outputs at least one error location corresponding to the calculated root, and generates an indication signal based on the result of the determination, and
wherein the memory controller further comprises:
a memory which stores the data input through the memory interface;
a correction direct memory access (DMA) which corrects an error included in each of the plurality of chunks stored in the memory using the at least one error location on each of the plurality of chunks and stores each of the error-corrected chunks in the memory; and
a host DMA which determines the output time of the error-corrected first chunk stored in the memory in response to an indication signal output from the ECC block.

6. The memory controller of claim 5 , wherein, if the ECC block determines that the coefficient of the each term is all zero, the host DMA outputs the error-corrected first chunk in response to the indication signal output from the ECC block while the ECC block calculates the root of the error location polynomial on the last chunk.

7. The memory controller of claim 5 , further comprising:
an OR gate which receives the indication signal which is output from the ECC block and an error correction completion signal which is output from the correction DMA and indicates that the error correction on the last chunk is completed, and performs an operation on the two signals to generate a transmission control signal,
wherein the host DMA controls the output time of the error-corrected first chunk based on the transmission control signal.

8. The memory controller of claim 5 , wherein the host DMA outputs the error-corrected first chunk output through a host interface to a host.

9. A memory controller comprising:
an interface unit through which data comprising a plurality of chunks is input, at least one of the plurality of chunks containing an error;
a memory which stores the data input through the interface unit; and
an error correction unit which controls a time to begin to output the plurality of chunks from the memory to a host by determining a coefficient value of at least one predetermined term of an error location polynomial for a last chunk in the plurality of chunks,
wherein the error correction unit corrects the error in the at least one chunk and outputs the plurality of chunks from the memory to the host, based on the time to begin to output the plurality of chunks,
wherein the error correction unit controls the time to begin to output the plurality of chunks by determining if a coefficient of each term of which a degree is equal to or greater than a degree of a reference-degree term, in the error location polynomial for the last chunk, is all zero,
wherein the error correction unit determines an output time of an error-corrected first chunk based on a result of the determining if the coefficient of the each term is all zero,
wherein the error correction unit outputs the error-corrected first chunk while a root of the error location polynomial for the last chunk is calculated or while error correction on the last chunk is performed using at least one error location corresponding to the calculated root, if it is determined that the coefficient of the each term is all zero, and
wherein the error correction unit performs error correction on the last chunk before outputting the error-corrected first chunk if it is determined that a coefficient of any term of which a degree is equal to or greater than the degree of the reference-degree term, in the error location polynomial for the last chunk among the plurality of chunks, is not zero.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kong Jae Phil
• Shin Soong Mann
• Choi Myung Suk
• Yang Sin Ho

Classifications

• G06F11/10 Primary

  Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's · CPC title

• G06F11/1052 Primary

  Bypassing or disabling error detection or correction · CPC title

• G11C7/10

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title

• G11C16/06

  Auxiliary circuits, e.g. for writing into memory · CPC title

• G11C7/22 Primary

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title