Transceiver multiplexing over USB type-C interconnects

Patent metadata

Field	Value
Publication number	US-9934176-B2
Application number	US-201414582785-A
Country	US
Kind code	B2
Filing date	Dec 24, 2014
Priority date	Dec 24, 2014
Publication date	Apr 3, 2018
Grant date	Apr 3, 2018

Abstract

An apparatus for transceiver multiplexing over USB Type-C interconnects is described herein. The apparatus includes a processor, a memory, a USB Type-C connector, a first transmitter, a multiplexed transmitter, a multiplexed receiver, and an on-die inductor. The multiplexed transmitter, when disabled, enables the multiplexed receiver to be in communication over a channel with a second transmitter over the USB Type C connector. The multiplexed receiver, when disabled, enables the multiplexed transmitter to be in communication over the channel with a receiver over the USB Type-C connector. The on-die inductor is disposed in serial with the multiplexed transmitter, and disposed in parallel with the multiplexed receiver. The on-die inductor reduces: effective shunt capacitance and insertion loss between the multiplexed transmitter and the channel; effective shunt capacitance and insertion loss between the channel and the multiplexed receiver.

First claim

What is claimed is:

1. An apparatus for transceiver multiplexing over a serial bus, the apparatus comprising:
a reversible, multi-mode, bi-directional power connector;
a first transmitter;
a multiplexed transmitter which, when disabled, is to enable a multiplexed receiver, to be in communication over a channel with a second transmitter over a USB Type C connector;
the multiplexed receiver which, when disabled, is to enable the multiplexed transmitter to be in communication over the channel with a receiver over the USB Type-C connector; and
an on-die inductor disposed:
in serial with the multiplexed transmitter; and
in parallel with the multiplexed receiver; and

a T-coil comprising:
a first inductor being disposed between the on-die inductor and a second inductor, wherein the first inductor is disposed between the multiplexed transmitter and the multiplexed receiver; and
the second inductor, being disposed between the first inductor and the channel.

2. The apparatus of claim 1 , the on-die inductor to reduce:
effective shunt capacitance and insertion loss between the multiplexed transmitter and the channel; and
effective shunt capacitance and insertion loss between the channel and the multiplexed receiver.

3. The apparatus of claim 1 , the reversible, multi-mode, bi-directional power connector being based on a universal serial bus (USB) Type-C specification.

4. The apparatus of claim 1 , the first transmitter and the multiplexed transmitter comprising 2 DisplayPort lanes.

5. The apparatus of claim 1 , the first transmitter and the multiplexed transmitter comprising 2 Mobile Industry Processor Interface lanes.

6. The apparatus of claim 1 , the first transmitter and the multiplexed receiver comprising a USB3.1 port.

7. The apparatus of claim 1 , the first transmitter and the multiplexed receiver comprising a Thunderbolt port.

8. The apparatus of claim 1 , the first transmitter and the multiplexed receiver comprising a PCIe port.

9. The apparatus of claim 1 , the first transmitter and the multiplexed receiver comprising a Mobile Industry Processor Interface port.

10. The apparatus of claim 1 , comprising a T-coil, the T-coil comprising:
a first arm, the on-die inductor being disposed between the first arm and the multiplexed transmitter;
a second arm connected with the channel; and
a middle tap connected with the multiplexed receiver, the multiplexed transmitter being a voltage-mode driver.

11. The apparatus of claim 1 , comprising a T-coil, the T-coil comprising:
a first arm, the on-die inductor being disposed between the first arm and the multiplexed receiver;
a second arm connected with the channel; and
a middle tap connected with the multiplexed transmitter, the multiplexed transmitter being a current-mode driver.

12. An apparatus for transceiver multiplexing over a serial bus, the apparatus comprising:
a reversible, multi-mode, bi-directional power connector;
a first transmitter;
a multiplexed transmitter which, when disabled, is to enable a multiplexed receiver, to be in communication over a channel with a second transmitter over the reversible, multi-mode, bi-directional power connector;
the multiplexed receiver which, when disabled, is to enable the multiplexed transmitter to be in communication over the channel with a receiver over the reversible, multi-mode, bi-directional power connector;
a T-coil comprising:
a first arm;
a second arm connected with the channel;
a middle tap;
a first inductor being disposed between an on-die inductor and a second inductor, wherein the first inductor is disposed between the multiplexed transmitter and the multiplexed receiver; and
the second inductor, being disposed between the first inductor and the channel; and
the on-die inductor to reduce:
effective shunt capacitance and insertion loss between the multiplexed transmitter and the channel; and
effective shunt capacitance and insertion loss between the channel and the multiplexed receiver.

13. The apparatus of claim 12 , the on-die inductor being disposed between the first arm and the multiplexed transmitter, and the multiplexed receiver being a voltage-mode driver.

14. The apparatus of claim 12 , the on-die inductor being disposed between the first arm and the multiplexed receiver, and the multiplexed transmitter being a current-mode driver.

15. The apparatus of claim 12 , the first transmitter and the multiplexed transmitter comprising 2 DisplayPort lanes.

16. The apparatus of claim 12 , the first transmitter and the multiplexed transmitter comprising 2 Mobile Industry Processor Interface transmitter lanes.

17. The apparatus of claim 12 , the first transmitter and the multiplexed receiver comprising a USB 3.1 port.

18. The apparatus of claim 12 , the first transmitter and the multiplexed receiver comprising a Thunderbolt port.

19. The apparatus of claim 12 , the first transmitter and the multiplexed receiver comprising a PCIe port.

20. The apparatus of claim 12 , the first transmitter and the multiplexed receiver comprising a Mobile Industry Processor Interface port.

21. The apparatus of claim 12 , the reversible, multi-mode, bi-directional power connector being based on a universal serial bus (USB) Type-C specification.

22. A method for transceiver multiplexing over a serial bus, the method comprising:
determining whether communication over a reversible, multi-mode, bi-directional power connector, is uni-directional or bi-directional, wherein the communication takes place over a channel that is connected with an inductor;
disabling a multiplexed receiver if the communication is uni-directional, the multiplexed receiver being multiplexed with a multiplexed transmitter, the multiplexed transmitter being connected with the inductor; and
disabling the multiplexed transmitter if the communication is bi-directional, wherein the multiplexed receiver is connected with a middle tap of a T-coil, the inductor being disposed between the multiplexed transmitter and a first arm of the T-coil, and wherein the channel is connected with a second arm of the T-coil, wherein the T-coil comprises:
a first inductor being disposed between an on-die inductor and a second inductor, wherein the first inductor is disposed between the multiplexed transmitter and the multiplexed receiver; and
the second inductor, being disposed between the first inductor and the channel.

23. The method of claim 22 , the reversible, multi-mode, bi-directional power connector being based on a universal serial bus (USB) Type-C specification.

Assignees

• Intel Corp

Inventors

• Wang Wei
• Tsai Hsiao-Ping J
• Park Jongbae

Classifications

• G06F13/287 Primary

  Multiplexed DMA (G06F13/30 takes precedence) · CPC title

• G06F13/4282 Primary

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/4086

  Bus impedance matching, e.g. termination · CPC title

• G06F13/4072

  Drivers or receivers (G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002) · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title