Reduced uncorrectable memory errors

Patent metadata

Field	Value
Publication number	US-9934088-B2
Application number	US-201514844843-A
Country	US
Kind code	B2
Filing date	Sep 3, 2015
Priority date	Mar 11, 2013
Publication date	Apr 3, 2018
Grant date	Apr 3, 2018

Abstract

Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.

First claim

What is claimed is:

1. A method to reduce uncorrectable memory errors comprising:
determining a logical array address for a set of memory arrays;
transforming the logical array address to at least two unique array addresses based, at least in part, on a logical location of at least two memory arrays within the set of memory arrays, transforming the logical array address includes at least one of:
rotating the logical array address by a number of locations based on the logical location;
rotating upper lines of the logical array address by a first multiple and rotating lower lines of the logical array address by a second multiple, different than the first multiple; or
adding a multiple of the logical location to the logical array address and discarding any additional upper bits; and
accessing the at least two memory arrays using the at least two unique array addresses, respectively;

wherein transforming to the at least two unique array addresses causes a reduction to uncorrectable errors for data included in an error correction codeword stored in the set of memory arrays.

2. The method of claim 1 , the error correction codeword comprises at least a bit of data, respectively, stored in memory arrays of the set of memory arrays; and
a common physical location in the at least two memory arrays is mapped to at least two different error correction codewords to reduce uncorrectable memory errors due to systemic errors in the set of memory arrays overloading the error correction codeword with errors.

3. The method of claim 1 , further comprising:
retrieving the error correction codeword stored in the set of memory arrays using the at least two unique array addresses; and
providing the error correction codeword to a controller the controller to correct one or more errors in the data included in the error correction codeword.

4. The method of claim 1 , a first unique array address comprises a first row address and a first column address; and
a second unique array address comprises a second row address and a second column address, the first row address is different than the second row address, or the first column address is different than the second column address.

5. The method of claim 1 , further comprising accessing a group of memory arrays within the set of memory arrays using a first unique array address of the at least two unique array addresses.

6. The method of claim 1 , the logical locations of the at least two memory arrays comprise identifiers of groups of memory arrays within the set of memory arrays.

7. The method of claim 6 , the logical locations of the at least two memory arrays further comprise chip identifiers.

8. The method of claim 1 , the set of memory arrays comprises a first memory array located on a first memory die and a second memory array located on a second memory die.

9. An integrated circuit comprising:
a set of memory arrays comprising at least a first memory array and a second memory array;
a first circuit to transform a logical array address into a first unique array address coupled to the first memory array based, at least in part, on a logical location of the first memory array within the set of memory arrays; and
a second circuit to transform the logical array address into a second unique array address coupled to the second memory array based, at least in part, on a logical location of the second memory array within the set of memory arrays, the second circuit is to perform operations that includes at least one of:
a rotation of the logical array address by a number of locations based on the logical location;
a rotation of upper lines of the logical array address by a first multiple and rotating lower lines of the logical array address by a second multiple, different than the first multiple; or
add a multiple of the logical location to the logical array address and discard any additional upper bits;

wherein data from the first memory array at the first unique array address and data from the second memory array at the second unique array address are included in a particular error correction codeword to reduce uncorrectable errors in data included the particular error correction codeword.

10. The integrated circuit of claim 9 , comprising:
a first error correction codeword that includes data identified by a first logical array address, and a second error correction codeword that includes data identified by a second logical array address;
the first circuit transforms a first logical address to identify a particular array location in the first memory array and the second circuit transforms a second logical address to identify the particular array location in the second memory array; and
a systemic error in the particular array location in both the first memory array and the second memory array distributes errors between the first error correction codeword and the second error correction codeword to avoid overloading either the first error correction codeword or the second error correction codeword with errors.

11. The integrated circuit of claim 9 , further comprising:
a data interface to provide the particular error correction codeword to a controller;
wherein the controller is configured to correct one or more errors in the data included in particular error correction codeword.

12. The integrated circuit of claim 9 , the first circuit comprises circuitry to re-order address lines of the logical array address.

13. The integrated circuit of claim 9 , the first circuit comprises circuitry to perform an arithmetic operation via use of the logical array address and at least a portion of the logical location of the first memory array within the set of memory arrays.

14. The integrated circuit of claim 13 , the second circuit comprises circuitry to perform the arithmetic operation via use of the logical array address and at least a portion of the logical location of the second memory array within the set of memory arrays.

15. The integrated circuit of claim 9 , the first circuit comprises circuitry to transform the logical array address based, in part, on values programmed into a control register.

16. The integrated circuit of claim 9 , the logical locations of the at least two memory arrays comprise identifiers of groups of memory arrays within the set of memory arrays.

17. The integrated circuit of claim 9 , further comprising a chip identifier input;
wherein the logical locations of the at least two memory arrays further comprise values received from the chip identifier input.

18. The integrated circuit of claim 9 , comprising:
the first memory array located on a first memory die; and
the second memory array located on a second memory die.

19. An electronic system comprising:
supervisory circuitry to generate memory read commands comprising a logical array address; and
a memory, coupled to the supervisory circuitry, to respond to the memory read commands, the memory comprising:
a set of memory arrays;
circuitry to transform the logical array address to at least two unique array addresses based, at least in part, on a logical location of at least two memory arrays within the set of memory arrays, the at least two unique array addresses coupled to the at least two memory arrays, respectively, the circuitry is to perform operations that includes at least one of:
a rotation of the logical array address by a number of locations based on the logical location;
a rotation of upper lines of the logical array address by a first multiple and rotating lower lines of the logical array addre

Assignees

• Intel Corp

Inventors

• Pangal Kiran
• Damle Prashant S
• Sundaram Rajesh
• Qawami Shekoufeh
• Walker Julie M
• Rivers Doyle

Classifications

• H03M13/152

  Bose-Chaudhuri-Hocquenghem [BCH] codes · CPC title

• H03M13/19

  Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes · CPC title

• H03M13/27

  using interleaving techniques · CPC title

• G06F3/064

  Management of blocks · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title