Photonic chip with an evanescent coupling interface

Patent metadata

Field	Value
Publication number	US-9933566-B2
Application number	US-201615143944-A
Country	US
Kind code	B2
Filing date	May 2, 2016
Priority date	Nov 13, 2015
Publication date	Apr 3, 2018
Grant date	Apr 3, 2018

Abstract

Embodiments herein describe a photonic chip which includes a coupling interface for evanescently coupling the chip to a waveguide on an external substrate. In one embodiment, the photonic chip includes a tapered waveguide that aligns with a tapered waveguide on the external substrate. The respective tapers of the two waveguides are inverted such that as the width of the waveguide in the photonic chip decreases, the width of the waveguide on the external substrate increases. In one embodiment, these two waveguides form an adiabatic structure where the optical signal transfers between the waveguides with minimal or no coupling of the optical signal to other non-intended modes. Using the two waveguides, optical signals can be transmitted between the photonic chip and the external substrate.

First claim

We claim:

1. An optical system, comprising:
a photonic chip, comprising:
an insulation layer,
an active surface layer directly contacting the insulation layer, wherein the active surface layer includes a first optical component optically coupled to a silicon waveguide, and
an evanescent coupler spaced apart from the silicon waveguide along a direction normal to the insulation layer and active surface layer, wherein the evanescent coupler is optically coupled to the silicon waveguide; and

an external optical device, comprising:
a second optical component,
a spot size converter coupled to the second optical component, wherein the spot size converter is configured to alter a mode size of optical signals transferred between the silicon waveguide and the second optical component, and
a coupling waveguide in the spot size converter, wherein a first end of the coupling waveguide overlaps a first end of the evanescent coupler along the direction normal to the insulation layer and active surface layer, wherein the first end of the coupling waveguide is inversely tapered relative to the first end of the evanescent coupler thereby evanescently coupling the photonic chip to the external optical device, and

wherein the photonic chip and the external optical device are bonded together along a coupling interface that is parallel to a plane where the insulation layer contacts the active surface layer.

2. The optical system of claim 1 , wherein the photonic chip further comprises:
an optical via disposed between the evanescent coupler and the silicon waveguide, wherein the optical via includes a plurality of waveguides disposed at different layers spaced apart along the direction normal to the insulation layer and active surface layer, and wherein portions of the plurality of waveguides are tapered to transfer optical signals between the evanescent coupler and the silicon waveguide.

3. The optical system of claim 2 , wherein the photonic chip further comprises:
a plurality of metal and via routing layers coupled to the first optical component, wherein the plurality of waveguides of the optical via are disposed on at least some of the plurality of metal and via routing layers.

4. The optical system of claim 1 , wherein the evanescent coupler is disposed on a first side of the insulation layer that is opposite a second side of the insulation layer that contacts the active surface layer, wherein a second end of the evanescent coupler overlaps a first end of the silicon waveguide along the direction normal to the insulation layer and active surface layer, and
wherein the second end of the evanescent coupler is inversely tapered relative to the first end of the silicon waveguide such that the evanescent coupler and the silicon waveguide are evanescently coupled.

5. The optical system of claim 4 , wherein the coupling interface and the external optical device are disposed on the first side of the insulation layer, wherein the photonic chip further comprises:
a through oxide via extending from the coupling interface, through the insulation layer, and through the active surface layer to connect to at least one metal layer coupled to the first optical component.

6. The optical system of claim 1 , wherein a width of the first end of the coupling waveguide decreases as the coupling waveguide extends along a first direction and a width of the first end of the evanescent coupler increases as the evanescent coupler extends along the first direction, thereby creating an inverse taper.

7. The optical system of claim 6 , wherein a gap between the first ends of the coupling waveguide and the evanescent coupler along the direction normal to the insulation layer and active surface layer is less than or equal to 500 nanometers.

8. The optical system of claim 1 , wherein the external optical device is bonded to the photonic chip at the coupling interface using at least one of an oxide-oxide bond, a solder collapse bond, and an epoxy collapse bond.

9. The optical system of claim 1 , wherein the second optical component is a light source configured to transmit light into the silicon waveguide through the spot size converter and evanescent coupler.

10. A photonic chip, comprising:
an insulation layer;
an active surface layer directly contacting the insulation layer, wherein the active surface layer includes a first optical component optically coupled to a silicon waveguide;
an evanescent coupler spaced apart from the silicon waveguide along a direction normal to the insulation layer and active surface layer, wherein the evanescent coupler is optically coupled to the silicon waveguide; and
a coupling interface parallel to a plane where the insulation layer contacts the active surface layer, wherein the evanescent coupler is within at least 500 nanometers of the coupling interface to permit the evanescent coupler to optically couple to an external optical device when the external optical device is bonded to the coupling interface.

11. The photonic chip of claim 10 , further comprising:
an optical via disposed between the evanescent coupler and the silicon waveguide, wherein the optical via includes a plurality of waveguides disposed at different layers spaced apart along the direction normal to the insulation layer and active surface layer, and wherein portions of the plurality of waveguides are tapered to transfer optical signals between the evanescent coupler and the silicon waveguide.

12. The photonic chip of claim 11 , further comprising:
a plurality of metal and via routing layers coupled to the first optical component, wherein the plurality of waveguides of the optical via are disposed on at least some of the plurality of metal and via routing layers.

13. The photonic chip of claim 10 , wherein the evanescent coupler is disposed on a first side of the insulation layer that is opposite a second side of the insulation layer that contacts the active surface layer, wherein a second end of the evanescent coupler overlaps a first end of the silicon waveguide along the direction normal to the insulation layer and active surface layer, and
wherein the second end of the evanescent coupler is inversely tapered relative to the first end of the silicon waveguide such that the evanescent coupler and the silicon waveguide are evanescently coupled.

14. The photonic chip of claim 13 , wherein the coupling interface is disposed on the first side of the insulation layer, wherein the photonic chip further comprises:
a through oxide via extending from the coupling interface, through the insulation layer, and through the active surface layer to connect to at least one metal layer coupled to the first optical component.

15. The photonic chip of claim 10 , wherein a width of a first end of the silicon waveguide decreases as the silicon waveguide extends along a first direction and a width of a first end of the evanescent coupler increases as the evanescent coupler extends along the first direction thereby creating an inverse taper.

16. A method, comprising:
providing a photonic chip comprising a first semiconductor substrate, an insulation layer contacting the first semiconductor substrate, an active surface layer contacting the insulation layer, and a plurality of metal routing layers electrically coupled to a first optical component in the active surface layer, and wherein the first optical component is optically coupled to a silicon waveguide in the active surface layer;
providing a wafer comprising an oxide layer disposed on a second semiconductor substrate;
bonding a first side of the oxide layer in the wafer to a first side

Assignees

• Cisco Tech Inc

Inventors

• Patel Vipulkumar
• Webster Mark
• Tummidi Ravi
• Nadeau Mary

Classifications

• G02B6/305

  and having an integrated mode-size expanding section, e.g. tapered waveguide · CPC title

• G02B6/4291

  by accessing the evanescent field of the light guide · CPC title

• G02B6/12002

  Three-dimensional structures · CPC title

• G02B6/124

  Geodesic lenses or integrated gratings · CPC title

• G02B6/125

  Bends, branchings or intersections · CPC title