Methods of designing a layout of a semiconductor device including field effect transistor and methods of manufacturing a semicondutor device using the same

Patent metadata

Field	Value
Publication number	US-9928333-B2
Application number	US-201615184227-A
Country	US
Kind code	B2
Filing date	Jun 16, 2016
Priority date	Jul 30, 2015
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

A method of designing a semiconductor device includes preparing a standard cell layout including a layout out a preliminary pin pattern in at least one interconnection layout, performing a routing step to connect the preliminary pin pattern to a high-level interconnection layout, and generating a pin pattern in the interconnection layout, based on hitting information obtained at the completion of the routing step. The pin pattern is smaller than the preliminary pin pattern.

First claim

What is claimed is:

1. A method of producing a layout of a semiconductor device, comprising:
providing a standard cell layout, the providing of the standard cell layout comprising creating a preliminary pin pattern of an interconnection layout of the standard cell layout in association with a lower metal layer of the semiconductor device;
performing a routing step to produce a high-level interconnection layout in which the preliminary pin pattern is connected to a high-level interconnection pattern, the high-level interconnection layout representative of an upper level metal interconnection of the semiconductor device disposed above the lower metal layer; and
converting the preliminary pin pattern into a postliminary pin pattern in a region of the interconnection layout of the standard cell layout, based on hitting information obtained upon the completion of the routing step, the postliminary pin pattern representative of a lower level metal interconnection of the lower metal layer of the semiconductor device,
wherein the postliminary pin pattern is smaller than the preliminary pin pattern.

2. The method of claim 1 , wherein the converting of the preliminary pin pattern into the postliminary pin pattern places the postliminary pin pattern in a region that was occupied by the preliminary pin pattern such that the postliminary pin pattern and the preliminary pin pattern occupy overlapping regions in the method of producing the layout.

3. The method of claim 1 , wherein the providing of the standard cell layout comprises:
providing a logic layout including logic transistors; and
laying out a lower via pattern to connect the logic layout to the preliminary pin pattern.

4. The method of claim 1 , wherein the laying out of the preliminary pin pattern comprises laying out ghost patterns, in which pin information for the routing step is contained, and
the converting of the preliminary pin pattern into the postliminary pin pattern comprises converting one of the ghost patterns that hits the high-level interconnection layout into the postliminary pin pattern.

5. The method of claim 1 , wherein the converting of the preliminary pin pattern into the postliminary pin pattern comprises preserving a first region of the preliminary pin pattern while removing a second region of the preliminary pin pattern, and
the first region comprises a first hitting region to be connected to the high-level interconnection layout.

6. The method of claim 1 , further comprising providing a plurality of cell layouts, each based on the standard cell layout,
wherein the cell layouts have different interconnection layouts from one another, and
the converting of the preliminary pin pattern into the postliminary pin pattern comprises replacing the standard cell layout with one of the cell layouts, based on the hitting information.

7. The method of claim 1 , further comprises laying out multiple ones of the standard cell layout, before the routing step.

8. A method of designing a layout of a semiconductor device, comprising:
providing a first standard cell layout and a second standard cell layout in a cell library, the providing of the first and second standard cell layouts comprising laying out a first preliminary pin pattern and a second preliminary pin pattern on the first and second standard cell layouts, respectively and each in association with a lower metal layer of the semiconductor device;
laying out the first and second standard cell layouts;
performing a routing step to connect the first and second preliminary pin patterns to high-level interconnection layouts each representative of an upper level metal interconnection of the semiconductor device disposed above the lower metal layer; and
converting the first and second preliminary pin patterns into a first pin pattern and a second pin pattern, respectively, based on hitting information obtained after the routing step, the first and second pin patterns representative of a lower level metal interconnection of the lower metal layer of the semiconductor device,
wherein the first and second preliminary pin patterns are the same as each other in terms of size and arrangement, and
the first and second pin patterns are different from each other in terms of size and arrangement.

9. The method of claim 8 , wherein each of the first and second standard cell layouts comprises the same logic layout with the same circuit.

10. The method of claim 8 , wherein each of the first and second pin patterns is smaller in size than each of the first and second preliminary pin patterns.

11. The method of claim 8 , wherein the hitting information on the first standard cell layout is different from that on the second standard cell layout.

12. The method of claim 8 , wherein the laying out of each of the first and second preliminary pin patterns comprises laying out ghost patterns, in which pin information for the routing step is contained, and
the converting of the first and second preliminary pin patterns into the first and second pin patterns comprises converting first and second ones of the ghost patterns into the first and second pin patterns, respectively, when the first and second ones of the ghost patterns hit the high-level interconnection layouts.

13. The method of claim 8 , wherein the generating the converting of the first and second preliminary pin patterns into the first and second pin patterns comprises preserving a first region of each of the first and second preliminary pin patterns and removing a second region of each of the first and second preliminary pin patterns, other than the first region, and
the first region comprises a hitting region to be connected to the high-level interconnection layouts.

14. The method of claim 8 , further comprising:
providing a plurality of first cell layouts, each corresponding to the first standard cell layout; and
providing a plurality of second cell layouts, each corresponding to the second standard cell layout,
wherein the plurality of the first cell layouts comprise different interconnection layouts, respectively,
the plurality of the second cell layouts comprise different interconnection layouts, respectively,
the converting of the first preliminary pin pattern into the first pin pattern comprises relaying out the first standard cell layout with one of the first cell layouts, based on the hitting information, and
the converting of the second preliminary pin pattern into the second pin pattern comprises relaying out the second standard cell layout with one of the second cell layouts, based on the hitting information.

15. A method of fabricating a semiconductor device, comprising:
a process of generating a device layout of a semiconductor device, wherein the process includes:
acquiring a standard cell layout that includes a layout of active elements and/or regions of the semiconductor device, and an interconnection layout including a preliminary pin pattern defining a region in the semiconductor device containing a location of a lower via to be electrically connected to at least one of the active components and/or regions,
performing a routing step comprising overlaying a high-level interconnection pattern and an upper via pattern on the standard cell layout, wherein the high-level interconnection pattern intersects the preliminary pin pattern and is representative of a high-level interconnection of the semiconductor device, and the upper via pattern is placed at the intersection of the high-level interconnection pattern and the preliminary pin pattern and represents the location of an upper via of the semiconductor device,
based on the r

Assignees

• Song Taejoong
• Baek Sanghoon
• Cho Sungwe
• Do Jung Ho
• Yang Giyoung
• Lim Jinyoung
• Samsung Electronics Co Ltd

Inventors

• Song Taejoong
• Baek Sanghoon
• Cho Sungwe
• Do Jung-Ho
• Yang Giyoung
• Lim Jinyoung

Classifications

• G06F30/394 Primary

  Routing (G06F30/396 takes precedence) · CPC title

• H01L27/11807

  Electricity · mapped topic

• H01L27/0207

  Electricity · mapped topic

• G06F17/5077 Primary

  Physics · mapped topic

• H10D89/10 Primary

  Integrated device layouts · CPC title