Automatic compilation method and framework for generating a layout of integrated memory-compute circuit
US-2024403527-A1 · Dec 5, 2024 · US
Considering compatibility of adjacent boundary regions for standard cells placement and routing
US8959472B1 · US · B1
| Field | Value |
|---|---|
| Publication number | US-8959472-B1 |
| Application number | US-201314039224-A |
| Country | US |
| Kind code | B1 |
| Filing date | Sep 27, 2013 |
| Priority date | Sep 27, 2013 |
| Publication date | Feb 17, 2015 |
| Grant date | Feb 17, 2015 |
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Abstract
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A method of generating an integrated circuit layout comprises a step of determining a placement of standard cells selected from a standard cell library while permitting boundary conflicts in which incompatible boundary regions of standard cells are placed next to each other. After determining routing connections between the standard cells, the integrated circuit layout is generated. The generation of the integrated circuit layout includes a mapping step of mapping at least one incompatible boundary region to an alternative boundary region to resolve at least one boundary conflict.
First claim
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We claim: 1. A computer-implemented method of generating an integrated circuit layout using a standard cell library defining a plurality of standard cells, each standard cell defining a functional component for including in the integrated circuit layout, the method comprising steps of: determining a placement of standard cells selected from the standard cell library while permitting one or more boundary conflicts in which incompatible boundary regions are placed adjacent to each o…
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- G06F30/392Primary
Physics · mapped topic
- G06F30/398Primary
Physics · mapped topic
- G06F30/394Primary
Physics · mapped topic
- G06F17/5072Primary
Physics · mapped topic
Physics · mapped topic
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- What does patent US8959472B1 cover?
- A method of generating an integrated circuit layout comprises a step of determining a placement of standard cells selected from a standard cell library while permitting boundary conflicts in which incompatible boundary regions of standard cells are placed next to each other. After determining routing connections between the standard cells, the integrated circuit layout is generated. The generat…
- Who is the assignee on this patent?
- Advanced Risc Mach Ltd
- What technology area does this patent fall under?
- Primary CPC classification G06F30/392. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Feb 17 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).