MEMS devices and methods of forming the same

Patent metadata

Field	Value
Publication number	US-9926190-B2
Application number	US-201615003332-A
Country	US
Kind code	B2
Filing date	Jan 21, 2016
Priority date	Jan 21, 2016
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

A MEMS device and methods of forming are provided. A dielectric layer of a first substrate is patterned to expose conductive features and a bottom layer through the dielectric layer. A first surface of a second substrate is bonded to the dielectric layer and the second substrate is patterned to form a membrane and a movable element. A cap wafer is bonded to the second substrate, where bonding the cap wafer to the second substrate forms a first sealed cavity comprising the movable element and a second sealed cavity that is partially bounded by the membrane. Portions of the cap wafer are removed to expose the second sealed cavity to ambient pressure.

First claim

What is claimed is:

1. A method for forming a micro-electromechanical systems (MEMS) device, the method comprising:
patterning a dielectric layer of a first substrate to expose conductive features and a bottom layer through the dielectric layer, the first substrate comprising the dielectric layer and the bottom layer, the conductive features being disposed in the dielectric layer on the bottom layer;
bonding a first surface of a second substrate to the dielectric layer;
patterning the second substrate to form a membrane and a movable element;
forming a first through via adjacent to the movable element;
forming a first plurality of metal bonds on a second surface of the second substrate, wherein the second surface is opposite the first surface, wherein the first plurality of metal bonds includes a first metal bond that is closest to the movable element, wherein the first through via is disposed between the movable element and a portion of second substrate on which the first metal bond is formed, and wherein the second substrate is continuous between the first through via and the portion of the second substrate on which the first metal bond is formed;
forming a second plurality of metal bonds on a surface of a cap wafer;
bonding the cap wafer to the second substrate by bonding the second plurality of metal bonds to the first plurality of metal bonds, wherein bonding the cap wafer to the second substrate forms a first sealed cavity and a second sealed cavity, the first sealed cavity comprising the movable element, and the second sealed cavity being partially bounded by the membrane; and
removing portions of the cap wafer to expose the second sealed cavity to ambient pressure.

2. The method of claim 1 , wherein bonding the cap wafer to the second substrate comprises a eutectic bonding process, wherein a pressure level of the first cavity after the bonding is defined by the eutectic bonding process.

3. The method of claim 1 , wherein bonding the second substrate to the first substrate comprises a fusion bonding process.

4. The method of claim 1 , wherein the first through via extends from at least one of the conductive features in the dielectric layer through the second substrate.

5. The method of claim 1 claim, further comprising forming a plurality of anti-stiction bumps that are positioned underneath the movable element.

6. The method of claim 1 , wherein removing portions of the cap wafer to expose the second sealed cavity to ambient pressure comprises forming an opening in the cap wafer to expose the second cavity to an ambient environment.

7. The method of claim 1 , wherein the bonding of the first surface of the second substrate to the dielectric layer creates a third sealed cavity, wherein a pressure level of the third cavity after the bonding is defined by the bonding process.

8. A method for forming a micro-electromechanical systems (MEMS) device comprising:
patterning a dielectric layer of a first substrate to create a first cavity and a second cavity, the first substrate comprising the dielectric layer and a bottom layer, a first electrode disposed on the bottom layer in the first cavity and a second electrode disposed on the bottom layer in the second cavity;
patterning the dielectric layer to expose a plurality of conductors, the conductors disposed in the dielectric layer on the bottom layer;
bonding a first surface of a second substrate to the dielectric layer, the bonding sealing the second cavity;
forming a plurality of through vias that extend from the conductors through the second substrate;
patterning the second substrate to create a movable feature, the movable feature positioned over the first electrode;
patterning the second substrate to create a membrane, the membrane positioned over the second electrode, wherein a first through via of the plurality of through vias and a second through via of the plurality of through vias are disposed adjacent to the membrane and on opposite sides of the membrane, a third through via of the plurality of through vias is disposed between the second through via and the movable feature, and wherein a portion of the second substrate that is between the second through via and the third through via is continuous along a line that extends from the second substrate to the third through via;
forming an opening in a third substrate;
bonding the third substrate to the second substrate in a manner that the opening in the third substrate is positioned over the membrane, wherein bonding the third substrate to the second substrate forms a third sealed cavity and a fourth sealed cavity, the third sealed cavity comprising the movable feature and the first cavity, and the fourth cavity being partially bounded by the membrane; and
removing portions of the third substrate to expose the fourth sealed cavity to ambient pressure through the opening in the third substrate.

9. The method of claim 8 , wherein a pressure level of the third sealed cavity is defined by a bonding process between the third substrate and the second substrate.

10. The method of claim 8 , wherein bonding the first surface of the second substrate to the dielectric layer comprises fusion bonding.

11. The method of claim 8 , further comprising forming a plurality of anti-stiction bumps over the first electrode.

12. The method of claim 8 , wherein bonding the third substrate to the second substrate comprises a eutectic bonding process between a first plurality of bonds disposed on the second substrate and a second plurality of bonds disposed on the third substrate.

13. A method for forming a micro-electromechanical systems (MEMS) device comprising:
bonding a first substrate to a second substrate, the bonding of the first substrate to the second substrate creating a first sealed cavity and a second sealed cavity, wherein a first conductive feature is exposed in the first sealed cavity and a second conductive feature is exposed in the second sealed cavity;
forming a plurality of bonds on a first surface of the second substrate;
depositing and patterning a first mask layer, the first mask layer being patterned to expose a section of the second substrate;
etching the second substrate through the patterned first mask layer to form a membrane overlying the first conductive feature, wherein the membrane is directly physically connected to a portion of the second substrate on which a closest bond of the plurality of bonds is formed;
depositing and patterning a second mask layer, the second mask layer being patterned to expose a plurality of sections of the second substrate;
etching the second substrate to form a movable element overlying the second conductive feature, wherein the etching of the second substrate unseals the second sealed cavity;
bonding a cap layer to the second substrate using the plurality of bonds to form a third sealed cavity and a fourth sealed cavity, the third sealed cavity comprising the movable element, the fourth cavity being defined in part by the membrane; and
thinning the cap layer to expose an opening in the cap layer, wherein exposing the opening in the cap layer unseals the fourth sealed cavity and exposes the membrane to ambient pressure.

14. The method according to claim 13 , further comprising thinning the second substrate after bonding the second substrate to the first substrate.

15. The method according to claim 13 , further comprising:
depositing and patterning a third mask layer over the second substrate, the third mask layer being patterned to expose portions of the second substrate;
etching the second substrate and the first substrate through the patterned third

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Kai-Fung
• Leu Len-Yi
• Tsai Lien-Yao

Classifications

• H10W72/07236

  Soldering or alloying · CPC title

• H10W20/023

  the interconnections being through-semiconductor vias · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H01L23/481

  Electricity · mapped topic

• B81C2203/0172

  Seals · CPC title