Scaling multi-core neurosynaptic networks across chip boundaries

Patent metadata

Field	Value
Publication number	US-9924490-B2
Application number	US-201314050072-A
Country	US
Kind code	B2
Filing date	Oct 9, 2013
Priority date	Oct 9, 2013
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

Embodiments of the invention provide a system for scaling multi-core neurosynaptic networks. The system comprises multiple network circuits. Each network circuit comprises a plurality of neurosynaptic core circuits. Each core circuit comprises multiple electronic neurons interconnected with multiple electronic axons via a plurality of electronic synapse devices. An interconnect fabric couples the network circuits. Each network circuit has at least one network interface. Each network interface for each network circuit enables data exchange between the network circuit and another network circuit by tagging each data packet from the network circuit with corresponding routing information.

First claim

What is claimed is:

1. A system for scaling multi-core neurosynaptic networks, comprising:
multiple neurosynaptic network circuits, wherein each network circuit comprises a plurality of neurosynaptic core circuits;
an interconnect fabric coupling said multiple network circuits; and
for each network circuit, at least one corresponding network interface, wherein each network interface for each network circuit enables data exchange between said network circuit and another network circuit of said multiple network circuits by:
tagging each outgoing data packet from said network circuit with a corresponding tag comprising:
source information indicative of a location of a source core circuit of said network circuit that generated said data packet; and
routing information including:
a first distance indicative of a first number of core circuits of said another network circuit that said outgoing data packet traverses horizontally within said another network circuit en route to a target core circuit of said another network circuit, wherein said outgoing data packet propagates along one of a first horizontal direction or a second horizontal direction opposite of the first horizontal direction if the first distance is one of a positive value or a negative value, respectively; and
a second distance indicative of a second number of core circuits of said another network circuit that said outgoing data packet traverses vertically within said another network circuit en route to said target core circuit of said another network circuit, wherein said outgoing data packet propagates along one of a first vertical direction or a second vertical direction opposite of the first vertical direction if the second distance is one of a positive value or a negative value, respectively;

wherein each core circuit comprises multiple electronic neurons, multiple electronic axons, and a plurality of electronic synapse devices for interconnecting said multiple neurons with said multiple axons.

2. The system of claim 1 , wherein each network interface for each network circuit further enables data exchange between said network circuit and another network circuit of said multiple network circuits by:
receiving incoming data packets for said network circuit;
de-serializing the incoming data packets; and
routing each incoming data packet to a target core circuit of said network circuit based on routing information included in a corresponding tag that said incoming data packet is tagged with, wherein said routing information comprises a horizontal distance field indicating a first number of core circuits of said network circuit that said incoming data packet traverses in an eastbound direction or a westbound direction to reach said target core circuit, and a vertical distance field indicating a second number of core circuits that said incoming data packet traverses in an eastbound direction or a westbound direction to reach said target core circuit.

3. The system of claim 2 , wherein each network interface for each network circuit further enables data exchange between said network circuit and another network circuit of said multiple network circuits by:
receiving outgoing data packets from said network circuit;
tagging each outgoing data packet with a corresponding tag including routing information, wherein said routing information comprises a horizontal distance field indicating a first number of core circuits of another network circuit of said multiple network circuits that said outgoing data packet traverses in an eastbound direction or a westbound direction to reach a target core circuit of said another network circuit, and a vertical distance field indicating a second number of core circuits that said outgoing data packet traverses in an eastbound direction or a westbound direction to reach said target core circuit;
merging the outgoing data packets; and
serializing the outgoing data packets.

4. The system of claim 3 , wherein:
each network interface for each network circuit comprises:
at least one funnel device for tagging and merging outgoing data packets from said network circuit; and
at least one device for serializing outgoing data packets from said network circuit and de-serializing incoming data packets for said network circuit.

5. The system of claim 3 , wherein data packets are exchanged between said multiple network circuits based on address event representation.

6. The system of claim 3 , wherein:
each data packet represents a neural firing event.

7. The system of claim 4 , wherein:
core circuits of each network circuit are arranged as a tillable array including multiple rows and multiple columns.

8. The system of claim 7 , wherein:
each funnel device for each network circuit is configured as a binary tree.

9. The system of claim 7 , wherein:
each funnel device for each network circuit is configured as a binary chain.

10. The system of claim 7 , wherein:
each funnel device for each network circuit is configured as both a binary tree and a binary chain.

11. A method for scaling multi-core neurosynaptic networks, comprising:
tagging data packets from multiple network circuits with routing information, wherein each network circuit has at least one corresponding network interface, and each network interface for each network circuit enables data exchange between said network circuit andanother network circuit of said multiple network circuits by tagging each outgoing data packet from said network circuit with a corresponding tag comprising:
source information indicative of a location of a source core circuit of said network circuit that generated said data packet; and
routing information including:
a first distance indicative of a first number of core circuits of said another network circuit that said outgoing data packet traverses horizontally within said another network circuit en route to a target core circuit of said another network circuit, wherein said outgoing data packet propagates along one of a first horizontal direction or a second horizontal direction opposite of the first horizontal direction if the first distance is one of a positive value or a negative value, respectively; and
a second distance indicative of a second number of core circuits of said another network circuit that said outgoing data packet traverses vertically within said another network circuit en route to said target core circuit of said another network circuit, wherein said outgoing data packet propagates along one of a first vertical direction or a second vertical direction opposite of the first vertical direction if the second distance is one of a positive value or a negative value, respectively; and

exchanging data packets between said multiple network circuits via an interconnect fabric coupling said multiple network circuits;
wherein each network circuit comprises a plurality of neurosynaptic core circuits; and
wherein each core circuit comprises multiple electronic neurons, multiple electronic axons, and a plurality of electronic synapse devices for interconnecting said multiple neurons with said multiple axons.

12. The method of claim 11 , further comprising:
for each network interface for each network circuit:
receiving incoming data packets for said network circuit;
de-serializing the incoming data packets; and
routing each incoming data packet to a target core circuit of said network circuit based on routing information included in a corresponding tag the said incoming data packet is tagged with, wherein said routing information comprises a horizontal distance field indicating a first number of core circuits of said network circuit that said incoming data packet tra

Assignees

• IBM

Inventors

• Alvarez Icaza Rivera Rodrigo
• Arthur John V
• Cassidy Andrew S
• Jackson Bryan L
• Merolla Paul A
• Modha Dharmendra S
• Sawada Jun

Classifications

• G06N3/063

  using electronic means · CPC title

• G06N3/049 Primary

  Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs · CPC title

• H04W64/00

  Locating users or terminals {or network equipment} for network management purposes, e.g. mobility management · CPC title

• H04W68/00 Primary

  User notification, e.g. alerting and paging, for incoming communication, change of service or the like · CPC title