Yield tolerance in a neurosynaptic system
US-11184221-B2 · Nov 23, 2021 · US
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Jackson Bryan L patents
Jackson Bryan L is listed as an inventor on 64 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Jackson Bryan L |
| Total patents | 64 |
| First publication | Feb 5, 2015 |
| Latest publication | Nov 23, 2021 |
Notable patents
Publications ranked by popularity score, then publication date.
Streaming programmable point mapper and compute hardware
US-11144553-B2 · Oct 12, 2021 · US
Event-based neural network with hierarchical addressing for routing event packets between core circuits of the neural network
US-11049001-B2 · Jun 29, 2021 · US
Event-based neural network with hierarchical addressing for routing event packets between core circuits of the neural network
US-2021166107-A1 · Jun 3, 2021 · US
Energy-efficient time-multiplexed neurosynaptic core for implementing neural networks spanning power- and area-efficiency
US-10990872-B2 · Apr 27, 2021 · US
Peripheral device interconnections for neurosynaptic systems
US-10984307-B2 · Apr 20, 2021 · US
Dual deterministic and stochastic neurosynaptic core circuit
US-10929747-B2 · Feb 23, 2021 · US
Implementing stochastic networks using magnetic tunnel junctions
US-10832151-B2 · Nov 10, 2020 · US
Scaling multi-core neurosynaptic networks across chip boundaries
US-10785745-B2 · Sep 22, 2020 · US
Converting digital numeric data to spike event data
US-10769519-B2 · Sep 8, 2020 · US
Recent patents
Latest publications not already listed above.
Converting spike event data to digital numeric data
US-10755165-B2 · Aug 25, 2020 · US
Interconnect circuits at three-dimensional (3-D) bonding interfaces of a processor array
US-10740282-B2 · Aug 11, 2020 · US
Coupling parallel event-driven computation with serial computation
US-10678741-B2 · Jun 9, 2020 · US
Utilizing a distributed and parallel set of neurosynaptic core circuits for neuronal computation and non-neuronal computation
US-10650301-B2 · May 12, 2020 · US
Yield tolerance in a neurosynaptic system
US-2019372831-A1 · Dec 5, 2019 · US
Yield tolerance in a neurosynaptic system
US-10454759-B2 · Oct 22, 2019 · US
Peripheral device interconnections for neurosynaptic systems
US-2019294950-A1 · Sep 26, 2019 · US
Peripheral device interconnections for neurosynaptic systems
US-10410109-B2 · Sep 10, 2019 · US
Event-based neural network with hierarchical addressing for routing event packets between core circuits of the neural network
US-10102474-B2 · Oct 16, 2018 · US
Yield tolerance in a neurosynaptic system
US-2018287862-A1 · Oct 4, 2018 · US
Dual deterministic and stochastic neurosynaptic core circuit
US-2018232634-A1 · Aug 16, 2018 · US
Interconnect circuits at three-dimensional (3-d) bonding interfaces of a processor array
US-2018189233-A1 · Jul 5, 2018 · US
Yield tolerance in a neurosynaptic system
US-9992057-B2 · Jun 5, 2018 · US
Dual deterministic and stochastic neurosynaptic core circuit
US-9984324-B2 · May 29, 2018 · US
Scaling multi-core neurosynaptic networks across chip boundaries
US-2018103448-A1 · Apr 12, 2018 · US
Interconnect circuits at three dimensional (3-D) bonding interfaces of a processor array
US-9940302-B2 · Apr 10, 2018 · US
Converting spike event data to digital numeric data
US-2018082174-A1 · Mar 22, 2018 · US
Converting digital numeric data to spike event data
US-2018082173-A1 · Mar 22, 2018 · US
Scaling multi-core neurosynaptic networks across chip boundaries
US-9924490-B2 · Mar 20, 2018 · US
Converting spike event data to digital numeric data
US-9886662-B2 · Feb 6, 2018 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| IBM | 65 |
| Jackson Bryan L | 2 |
| Modha Dharmendra S | 2 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06N3/063 | 33 |
| G06N3/049 | 28 |
| G06N3/04 | 19 |
| G06N3/0499 | 13 |
| G06N3/06 | 8 |