Pipelined SAR with TDC converter

Patent metadata

Field	Value
Publication number	US-9923568-B2
Application number	US-201715590247-A
Country	US
Kind code	B2
Filing date	May 9, 2017
Priority date	Dec 4, 2015
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

An analog-to-digital converter (ADC) that uses voltage-based signal processing and time-based signal processing to convert an analog input signal to a digital output signal is disclosed. In some embodiments, the ADC has a voltage-based signal processing element configured to receive an input signal and to generate a first digital signal having a plurality of most significant bits and a residue voltage. A residue offset circuit is configured to provide a residue offset voltage to the residue voltage. A voltage-to-time conversion element is configured to convert a sum of the residue voltage and the residue offset voltage to a time domain representation, and a time-based signal processing element is configured to convert the time domain representation to a second digital signal having a plurality of least significant bits.

First claim

What is claimed is:

1. An analog-to-digital converter (ADC), comprising:
a voltage-based signal processing element configured to receive an input signal and to generate a first digital signal having a plurality of most significant bits and a residue voltage;
a residue offset circuit configured to provide a residue offset voltage to the residue voltage;
a voltage-to-time conversion element configured to convert a sum of the residue voltage and the residue offset voltage to a time domain representation; and
a time-based signal processing element configured to convert the time domain representation to a second digital signal having a plurality of least significant bits.

2. The ADC of claim 1 , wherein the residue offset circuit comprises a capacitive element selectively coupled to a ground potential by way of a first switching element and to an offset voltage source by way of a second switching element.

3. The ADC of claim 1 , wherein the voltage-to-time conversion element, comprises:
an amplifier configured to generate an amplified residue voltage by amplifying the sum of the residue voltage and the residue offset voltage; and
a zero crossing detector configured to receive the amplified residue voltage and to generate the time domain representation from the amplified residue voltage.

4. The ADC of claim 3 , wherein the amplifier has an input coupled to an output of the voltage-based signal processing element and an output directly coupled to an input of the zero crossing detector.

5. The ADC of claim 4 , further comprising:
a discharge current source coupled to an output of the voltage-based signal processing element, the input of the amplifier, and an output of the residue offset circuit.

6. The ADC of claim 5 , further comprising:
a switching element coupled between the discharge current source and the amplifier.

7. The ADC of claim 1 , wherein the residue offset circuit is downstream of the voltage-based signal processing element.

8. The ADC of claim 1 , wherein the time-based signal processing element comprises:
a tapped delay line comprising a plurality of delay elements arranged in series to a pulse generator;
a plurality of flip-flops, wherein the plurality of delay elements respectively have an output coupled to a corresponding one of the plurality of flip-flops; and
a thermometer code converter coupled to outputs of the plurality of flip-flops and configured to generate the second digital signal.

9. An analog-to-digital converter (ADC), comprising:
a voltage-based signal processing element configured to receive an input signal and to generate a first digital signal having a first number of most significant bits and a residue voltage;
a voltage-to-time conversion element configured to convert the residue voltage to a time domain representation by discharging the residue voltage over a time that is proportional to the residue voltage;
a time-based signal processing element configured to convert the time domain representation to a second digital signal comprising a second number of least significant bits;
a digital error correction element configured to receive the first digital signal and the second digital signal and to generate a digital output signal therefrom, wherein the digital output signal has a third number of bits that is less than a sum of the first number and the second number; and
a residue offset circuit configured to cause the residue voltage to discharge in one direction regardless of whether the residue voltage is positive or negative.

10. The ADC of claim 9 , further comprising:
a discharge current source configured to selectively generate a discharge current that is configured to cause the residue voltage to discharge from the voltage-based signal processing element.

11. The ADC of claim 10 , wherein the voltage-to-time conversion element comprises:
an amplifier configured to generate an amplified residue voltage by amplifying the residue voltage; and
a zero crossing detector configured to receive the amplified residue voltage and to generate the time domain representation from the amplified residue voltage.

12. The ADC of claim 11 , further comprising:
a switching element coupled between the discharge current source and the amplifier.

13. The ADC of claim 11 , wherein the amplifier has an input coupled to an output of the voltage-based signal processing element and an output directly coupled to an input of the zero crossing detector.

14. The ADC of claim 13 , wherein the time domain representation comprises a pulse having a width that is a proportional to a value of the residue voltage.

15. The ADC of claim 11 ,
wherein the residue offset circuit is coupled between an output of the voltage-based signal processing element and an input of the voltage-to-time conversion element.

16. The ADC of claim 15 , wherein the discharge current source is coupled to an output of the voltage-based signal processing element, an input of the amplifier, and an output of the residue offset circuit.

17. A method of performing an analog to digital conversion, comprising:
generating a first digital signal having a first number of most significant bits based upon an analog input signal;
determining a residue voltage based upon the first digital signal;
adding a residue offset voltage to the residue voltage;
converting a sum of the residue voltage and the residue offset voltage to a time domain representation; and
converting the time domain representation to a second digital signal having a second number of least significant bits.

18. The method of claim 17 , further comprising:
combining the first digital signal and the second digital signal to generate a digital output signal having a value corresponding to the analog input signal, wherein the digital output signal has a third number of bits that is less than a sum of the first number and the second number.

19. The method of claim 17 ,
wherein the residue offset voltage is generated by a residue offset circuit comprising a capacitive element coupled to a ground potential by way of a first switching element and to an offset voltage source by way of a second switching element; and
wherein the first switching element is operated by a first switching signal at a first time and the second switching element is operated by a second switching signal at a second time after the first time.

20. The method of claim 19 , further comprising:
operating a discharge current source to generate a discharge current, wherein the discharge current source is coupled to the residue offset circuit by a third switching element; and
wherein the third switching element is operated by a third switching signal at a third time after the second time.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Kinyua Martin

Classifications

• H03M1/1245

  Details of sampling arrangements or methods · CPC title

• H03M1/54

  Input signal sampled and held with linear return to datum · CPC title

• H03M1/0607 Primary

  Offset or drift compensation (removal of offset already present on the analogue input signal H03M1/1295) · CPC title

• H03M1/468 Primary

  in which the input S/H circuit is merged with the feedback DAC array · CPC title

• G04F10/005

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title