Method of minimizing the operating voltage of an SRAM cell

Patent metadata

Field	Value
Publication number	US-9390786-B2
Application number	US-201514813278-A
Country	US
Kind code	B2
Filing date	Jul 30, 2015
Priority date	Aug 13, 2014
Publication date	Jul 12, 2016
Grant date	Jul 12, 2016

Abstract

An SRAM cell is formed of FDSOI-type NMOS and PMOS transistors. A doped well extends under the NMOS and PMOS transistors and is separated therefrom by an insulating layer. A bias voltage is applied to the doped well. The applied bias voltage is adjusted according to a state of the memory cell. For example, a temperature of the memory cell is sensed and the bias voltage adjusted as a function of the sensed temperature. The adjustment in the bias voltage is configured so that threshold voltages of the NMOS and PMOS transistors are substantially equal to n and p target threshold voltages, respectively.

First claim

The invention claimed is:

1. An integrated SRAM memory cell, comprising:
a silicon on insulator substrate including a semiconductor layer, an insulating layer and a semiconductor support;
an n-channel transistor having source, channel and drain regions formed in said semiconductor layer;
a p-channel transistor having source, channel and drain regions for in said semiconductor layer;
a doped well region in said semiconductor support located under said n- and p-channel transistors; and
a circuit configured to apply a variable bias voltage to said doped well region, wherein said circuit is configured to:
carry out measurements representative of a threshold voltage of the n-channel transistor and of a threshold voltage of the p-channel transistor; and
adjust the variable bias voltage so that the threshold voltages of the n-channel transistor and of the p-channel transistor are substantially equal to n and p target threshold voltages, respectively.

2. The integrated SRAM memory cell of claim 1 , wherein said circuit comprises:
a temperature sensor configured to sense a temperature of said integrated SRAM memory cell; and
a bias voltage generator configured to generate said variable bias voltage as a function of said sensed temperature.

3. The integrated SRAM memory cell of claim 2 , wherein the bias voltage generator compares the sensed temperature to a reference temperature and controls the variable bias voltage in response to a difference between the sensed and reference temperatures so as to correct for increases of operating voltage resulting from a variation of said difference.

4. The integrated SRAM memory cell of claim 2 , wherein the bias voltage generator is operable to increase the variable bias voltage when the sensed temperature decreases, and decreased the variable bias voltage when the sensed temperature increases.

5. The integrated SRAM memory cell of claim 1 , wherein substantially equal means within 10% of the n and p target threshold voltages.

6. The integrated SRAM memory cell of claim 1 , wherein the n and p target threshold voltages are equal to each other.

7. The integrated SRAM memory cell of claim 1 , wherein the measurement representative of the threshold voltages comprises a measurement of a frequency of an oscillator formed of a chain of inverters.

8. The integrated SRAM memory cell of claim 7 , wherein the chain of inverters are formed above said doped well located below said n-channel and p-channel transistors.

9. The integrated SRAM memory cell of claim 7 , wherein the chain of inverters is formed from n-channel and p-channel transistors identical to the n-channel and p-channel transistors of said SRAM memory cell.

10. The integrated SRAM memory cell of claim 1 , further comprising:
logic circuitry formed in said semiconductor layer; and
an additional doped well region in said semiconductor support located under said logic circuitry.

11. The integrated SRAM memory cell of claim 1 , wherein the n-channel and p-channel transistors are formed above a same doped well.

12. A method of minimizing an operating voltage of an SRAM cell formed of FDSOI-type NMOS and PMOS transistors, wherein a doped well extends under an insulating layer below the FDSOI-type transistors, comprising:
applying a bias voltage to the doped well,
carrying out measurements representative of a threshold voltage of the NMOS transistors and of a threshold voltage of the PMOS transistors, and
adjusting the bias voltage of the doped well according to a state of the memory cell so that the threshold voltage of the NMOS transistors and of the PMOS transistors are substantially equal to target threshold voltage of NMOS and PMOS transistors, respectively.

13. The method of claim 12 , wherein the memory cell is an element of an array of identical memory cells, the doped well being shared in common to all the memory cells in the array.

14. The method of claim 12 , wherein substantially equal means to within 10% of the target threshold voltage of NMOS and PMOS transistors.

15. The method of claim 12 , wherein the target threshold voltage of NMOS and PMOS transistors are equal.

16. The method of claim 12 , further comprising the successive steps of:
measuring an operating temperature of the memory cell; and
controlling the bias voltage in accordance with a difference between the operating temperature and a reference temperature so as to correct for increases of the operating voltage resulting from a variation of said difference.

17. The method of claim 16 , wherein the well is P-type doped and the bias voltage is increased when the operating temperature decreases, and the bias voltage is decreased when the operating temperature increases.

18. The method of claim 12 , wherein the measurement representative of the threshold voltages is a measurement of a frequency of an oscillator formed of a chain of inverters.

Assignees

• St Microelectronics Sa
• St Microelectronics Int Nv

Inventors

• Lecocq Christophe
• Akyel Kaya Can
• Chhabra Amit
• Dipti Dibya

Classifications

• G11C11/417 Primary

  for memory cells of the field-effect type · CPC title

• H01L27/1104

  Electricity · mapped topic

• G11C11/412

  using field-effect transistors only · CPC title

• H10B10/12

  comprising a MOSFET load element · CPC title