Operational amplifier circuit and bias current supply method

Patent metadata

Field	Value
Publication number	US-9923522-B2
Application number	US-201415305462-A
Country	US
Kind code	B2
Filing date	Jul 8, 2014
Priority date	Jul 8, 2014
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

Bias current is supplied to a first differential pair and a second differential pair from a first transistor being a single current source. Bias current is supplied to a third differential pair and a fourth differential pair from a second transistor being a single current source. An input voltage is at a power supply potential, and an input voltage is at a ground potential. When the second differential pair and the third differential pair are turned OFF, the bias current supplied from the first transistor flows to an output stage via the first differential pair, and the bias current supplied from the second transistor flows to the output stage via the fourth differential pair. Therefore, when the second differential pair and the third differential pair are turned OFF, a circuit current is kept constant, and a fluctuation in a frequency characteristic can be restrained.

First claim

The invention claimed is:

1. An operational amplifier circuit comprising:
a first parallel unit including a first differential pair configured with two field effect transistors having a same channel that is either N-channel or P-channel and a second differential pair configured with two field effect transistors channels of which are different from those of the first differential pair and connected to the first differential pair in parallel;
a second parallel unit including a third differential pair configured with two field effect transistors channels of which are same as those of the first differential pair and a fourth differential pair configured with two field effect transistors channels of which are same as those of the second differential pair and connected to the third differential pair in parallel;
a first current source to supply bias current to the first differential pair and the third differential pair;
a second current source to supply bias current to the second differential pair and the fourth differential pair;
an active load connected to the first parallel unit and the second parallel unit and in the first parallel unit and the second parallel unit,
a drain of the one of the field effect transistors in the first differential pair and a drain of the one of the field effect transistors in the third differential pair are short-circuited and connected to the active load,
a drain of the other one of the field effect transistors in the first differential pair and a drain of the other one of the field effect transistors in the third differential pair are short-circuited and connected to the active load,
a drain of the one of the field effect transistors in the second differential pair and a drain of the one of the field effect transistors in the fourth differential pair are short-circuited and connected to the active load, and
a drain of the other one of the field effect transistors in the second differential pair and a drain of the other one of the field effect transistors in the fourth differential pair are short-circuited and connected to the active load.

2. The operational amplifier circuit according to claim 1 ,
wherein source terminals of the two field effect transistors in the first differential pair are short-circuited to each other,
source terminals of the two field effect transistors in the third differential pair are short-circuited to each other,
the first current source supplies the bias current to each of the short-circuited source terminals,
source terminals of the two field effect transistors in the second differential pair are short-circuited to each other,
source terminals of the two field effect transistors in the fourth differential pair are short-circuited to each other, and
the second current source supplies the bias current to each of the short-circuited source terminals.

3. The operational amplifier circuit according to claim 1 ,
wherein the first current source includes a transistor that supplies the bias current to the first differential pair and the third differential pair, and
the second current source includes a transistor that supplies the bias current to the second differential pair and the fourth differential pair.

4. The operational amplifier circuit according to claim 1 ,
wherein in the first parallel unit,
in each differential pair, a gate terminal of one of the field effect transistors configuring each differential pair is connected to a first inverting input terminal disposed as an inverting input terminal, and in each differential pair, a gate terminal of the other one of the field effect transistors configuring each differential pair is connected to a first non-inverting input terminal disposed as a non-inverting input terminal, and
in the second parallel unit,
in each differential pair, a gate terminal of one of the field effect transistors configuring each differential pair is connected to a second inverting input terminal disposed as an inverting input terminal, and in each differential pair, a gate terminal of the other one of the field effect transistors configuring each differential pair is connected to a second non-inverting input terminal disposed as a non-inverting input terminal.

5. The operational amplifier circuit according to claim 1 ,
wherein the first differential pair and the third differential pair are configured with N-channel field effect transistors,
the second differential pair and the fourth differential pair are configured with P-channel filed effect transistors, and
the active load includes:
a first load unit having four cascode connected P-channel field effect transistors and connected to the first differential pair and the third differential pair; and
a second load unit having four cascode connected N-channel field effect transistors and connected the second differential pair and the fourth differential pair.

6. The operational amplifier circuit according to claim 1 , further comprising a voltage amplifier circuit connected to output terminals of the active load.

7. The operational amplifier circuit according to claim 6 ,
wherein the active load includes
an inverting output terminal outputting an inverting output voltage and a non-inverting output terminal outputting a non-inverting output voltage, and
the voltage amplifier circuit being a source grounded voltage amplifier circuit includes
a field effect transistor a gate terminal of which is applied with the inverting output voltage of the inverting output terminal and a source terminal of which is grounded and a field effect transistor a gate terminal of which is applied with the non-inverting output voltage of the non-inverting output terminal and a source terminal of which is grounded.

8. An operational amplifier circuit comprising:
a first parallel unit including a first differential pair configured with two field effect transistors having a same channel that is either N-channel or P-channel and a second differential pair configured with two field effect transistors channels of which are different from those of the first differential pair and connected to the first differential pair in parallel;
a second parallel unit including a third differential pair configured with two field effect transistors channels of which are same as those of the first differential pair and a fourth differential pair configured with two field effect transistors channels of which are same as those of the second differential pair and connected to the third differential pair in parallel;
a first current source to supply bias current to the first differential pair and the third differential pair;
a second current source to supply bias current to the second differential pair and the fourth differential pair;
a first active load connected to the first parallel unit;
a second active load connected to the second parallel unit, and
in the first parallel unit,
drains of the field effect transistors in the first differential pair and the second differential pair are connected to the first active load, and
in the second parallel unit,
drains of the field effect transistors in the third differential pair and the fourth differential pair are connected to the second active load.

9. The operational amplifier circuit according to claim 8 ,
wherein the first active load includes:
a first connection unit having four cascode connected field effect transistors and connected to the drain of the one of the field effect transistors in the first differential pair and the drain of the other one of the field effect transistors in the first differential pair; and
a second connection unit having four cascode connected field effect transistors and connected to the drain of the one of the field effect trans

Assignees

• Mitsubishi Electric Corp

Inventors

• Nakai Takayuki

Classifications

• H03F3/45748 Primary

  by using a feedback circuit · CPC title

• H03F1/0233 Primary

  by using a signal derived from the output signal, e.g. bootstrapping the voltage supply · CPC title

• H03F3/45219

  Folded cascode stages · CPC title

• H03F3/45475

  using IC blocks as the active amplifying circuit · CPC title

• H03F1/0277

  Selecting one or more amplifiers from a plurality of amplifiers · CPC title