DC offset cancellation circuit

Patent metadata

Field	Value
Publication number	US-9859857-B2
Application number	US-201715488365-A
Country	US
Kind code	B2
Filing date	Apr 14, 2017
Priority date	Apr 15, 2016
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

Disclosed herein is a DC offset cancellation circuit. The DC offset cancellation circuit includes a DC feedback unit configured to vary a DC feedback (DCFB) bandwidth to add at least one mid-bandwidth to the DCFB bandwidth and to provide a delay time in each case in order to reduce the DC droop error that occurs in switching from the high bandwidth (BW) to the mid-BW or from the mid-BW mode to the low BW mode, such that stable settling is ensured.

First claim

What is claimed is:

1. A DC offset cancellation circuit comprising:
an input signal stage for receiving an input signal;
a first amplifier for receiving the input signal, amplifying the input signal and outputting the amplified signal;
a DC feedback unit for receiving and filtering the amplified signal to extract and output a DC component of the amplified signal and feeding back the DC component to the first amplifier to change a DC feedback (DCFB) bandwidth to cancel a DC offset of the first amplifier; and
a controller for generating a control signal for changing the DCFB bandwidth by adjusting a delay and transmitting the control signal to the DC feedback unit to reduce a DC kick voltage generated according to change in the DCFB bandwidth.

2. The DC offset cancellation circuit according to claim 1 , wherein the controller operates in a high bandwidth mode within a period for an Automatic Gain Control (AGC) operation such that the DC offset cancellation circuit is locked within a predetermined time.

3. The DC offset cancellation circuit according to claim 1 , wherein the controller operates in a low bandwidth mode after the AGC operation is locked.

4. The DC offset cancellation circuit according to claim 1 , wherein the controller comprises a delay cell for providing a delay to secure a settling time of the DC offset cancellation circuit.

5. The DC offset cancellation circuit according to claim 1 , wherein the DC feedback unit provides at least one mid-bandwidth to the DCFB bandwidth to reduce the DC kick voltage.

6. The DC offset cancellation circuit according to claim 1 , wherein the DC feedback unit comprises:
an input stage for receiving a first output signal from the first amplifier;
a second amplifier having a second input stage and a second output stage, the second amplifier being a full differential amplifier;
a first variable resistor connected between a positive terminal of the input stage and a positive terminal of the second input stage of the second amplifier to change the DCFB bandwidth using the control signal;
a second variable resistor connected between a negative terminal of the input stage and a negative terminal of the second input stage of the second amplifier to change the DCFB bandwidth using the control signal;
a first capacitor connected between the positive terminal of the second input stage of the second amplifier and a negative terminal of the second output stage of the second amplifier to integrate a current flowing through the first variable resistor; and
a second capacitor connected between the negative terminal of the second input stage of the second amplifier and a positive terminal of the second output stage of the second amplifier to integrate a current flowing through the second variable resistor.

7. The DC offset cancellation circuit according to claim 6 , wherein the DC feedback unit further comprises:
a third resistor connected between the negative terminal of the second output stage of the second amplifier and a negative terminal of the output stage to shift the DCFB bandwidth; and
a fourth resistor connected between the positive terminal of the second output stage of the second amplifier and a positive terminal of the output stage to shift the DCFB bandwidth.

8. A method for cancelling a DC offset in a communication receiver including an amplifier, a DC feedback unit and a controller, the method comprising:
a receiving operation of receiving an input signal;
an amplifying operation of receiving the input signal, amplifying the input signal and outputting the amplified signal;
a bandwidth changing operation of receiving and filtering the amplified signal, extracting and outputting a DC component of the amplified signal, feeding back the DC component to the amplifier and changing a DC feedback (DCFB) bandwidth to cancel the DC offset of the amplifier; and
a control operation of adjusting a delay and transmitting a control signal for changing the DCFB bandwidth to the DC feedback unit to reduce a DC kick voltage generated according to change in the DCFB bandwidth.

9. The method according to claim 8 , wherein, in the control operation comprises:
the controller operating in a high bandwidth mode within a period for an Automatic Gain Control (AGC) operation such that the DC offset cancellation circuit is locked within a predetermined time.

10. The method according to claim 8 , wherein the control operation comprises:
the controller operating in a low bandwidth mode after the AGC operation is locked.

11. The method according to claim 8 , wherein the control operation further comprises:
a delay operation of providing a delay to secure a settling time of the DC offset cancellation circuit.

12. The method according to claim 8 , wherein the changing operation comprises:
providing at least one mid-bandwidth to the DCFB bandwidth to reduce the DC kick voltage.

Assignees

• Fci Inc

Inventors

• Jeong Seonghun

Classifications

• H03F2203/45521

  the FBC comprising op amp stages, e.g. cascaded stages of the dif amp and being coupled between the LC and the IC · CPC title

• H03G2201/202

  being in baseband · CPC title

• H04B1/62

  for providing a predistortion of the signal in the transmitter and corresponding correction in the receiver, e.g. for improving the signal/noise ratio · CPC title

• H03F2200/294

  the amplifier being a low noise amplifier [LNA] · CPC title

• H04B2001/305

  using DC offset compensation techniques · CPC title